- 专利标题: PRIORITIZATION OF ERROR CONTROL OPERATIONS AT A MEMORY SUB-SYSTEM
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申请号: US16533328申请日: 2019-08-06
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公开(公告)号: US20210042181A1公开(公告)日: 2021-02-11
- 发明人: Vamsi Pavan Rayaprolu , Harish R. Singidi , Kishore Kumar Muchherla , Ashutosh Malshe , Xiangang Luo
- 申请人: MICRON TECHNOLOGY, INC.
- 申请人地址: US ID Boise
- 专利权人: MICRON TECHNOLOGY, INC.
- 当前专利权人: MICRON TECHNOLOGY, INC.
- 当前专利权人地址: US ID Boise
- 主分类号: G06F11/07
- IPC分类号: G06F11/07
摘要:
A memory access operation can be determined to have failed. A determination can be made as to whether a performance of a first error control operation has remedied the failure of the memory access operation. In response to determining that the first error control operation has remedied the failure of the memory access operation, an order of a performance of one or more prioritized error control operations of the plurality of prioritized error control operations can be changed for a subsequent memory access operation that has failed based on the first error control operation that has remedied the failure.