Invention Application
- Patent Title: METHODS AND APPARATUS TO IMPROVE PERFORMANCE OF POWER PATH PROTECTION DEVICES
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Application No.: US17011522Application Date: 2020-09-03
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Publication No.: US20210066909A1Publication Date: 2021-03-04
- Inventor: Yogesh Kumar Ramadass , Ujwal Radhakrishna , Jeffrey Morroni
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Main IPC: H02H7/20
- IPC: H02H7/20 ; H01L23/525 ; H03K17/687

Abstract:
An example integrated circuit includes: a substrate and a first metal fuse layer on the substrate, the first metal fuse layer having first and second electrical contacts, the first electrical contact adapted to be coupled to an input terminal, the second electrical contact adapted to be coupled to a diode. The example integrated circuit further includes a second metal fuse layer on the substrate, the second metal fuse layer having third and fourth electrical contacts, the third electrical contact coupled to the second electrical contact and adapted to be coupled to the diode, the fourth electrical contact coupled to a shunt circuit.
Public/Granted literature
- US11824345B2 Methods and apparatus to improve performance of power path protection devices Public/Granted day:2023-11-21
Information query
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