Invention Application
- Patent Title: ANTI-AGING ARCHITECTURE FOR POWER MOSFET DEVICE
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Application No.: US16561670Application Date: 2019-09-05
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Publication No.: US20210074835A1Publication Date: 2021-03-11
- Inventor: Alberto CATTANI , Alessandro GASPARINI
- Applicant: STMicroelectronics S.r.l.
- Applicant Address: IT Agrate Brianza (MB)
- Assignee: STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics S.r.l.
- Current Assignee Address: IT Agrate Brianza (MB)
- Main IPC: H01L29/739
- IPC: H01L29/739 ; H02M1/32 ; H02M3/158
Abstract:
A power MOS stage includes a first power MOS device and a second power MOS devices connected in parallel between a first node and a second node, the first power MOS device having a first voltage rating and the second power MOS device having a second voltage rating that is lower than the first voltage rating. A driver circuit is configured to drive control nodes of the first and second power MOS devices in a sequential manner when actuating the power MOS stage by actuating the first power MOS device before actuating the second power MOS device. The control nodes of the first and second power MOS devices are further driven in a sequential manner when deactuating the power MOS stage by deactuating the second power MOS device before deactuating the first power MOS device.
Public/Granted literature
- US11094807B2 Anti-aging architecture for power MOSFET device Public/Granted day:2021-08-17
Information query
IPC分类:
