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1.发明申请公开(公告)号：US20230034786A1
公开(公告)日：2023-02-02
申请号：US17869508
申请日：2022-07-20
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro DAGO , Alessandro GASPARINI , Osvaldo Enrico ZAMBETTI , Salvatore LEVANTINO , Massimo Antonio GHIONI
Abstract: First and second circuit branches are coupled between an input node and ground. Each circuit branch includes a series coupling first-fourth transistors in a current flow path with an output node. A first capacitor is coupled between a first capacitor node and a second capacitor node intermediate the first transistor and the second transistor in the first circuit branch. A second capacitor is coupled between a third capacitor node and a fourth capacitor node intermediate the first transistor and the second transistor in the second circuit branch. An inter-branch circuit block between the first and second branches includes a first inter-branch transistor coupled between the first capacitor node in the first circuit branch and the fourth capacitor node in the second circuit branch and a second inter-branch transistor coupled between the third capacitor node in the second circuit branch and the second capacitor node in the first circuit branch.
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2.发明申请SYSTEM FOR DRIVING AN ARRAY OF MEMS STRUCTURES AND CORRESPONDING DRIVING METHOD 有权用于驱动MEMS结构阵列和相应驱动方法的系统公开(公告)号：US20150344295A1
公开(公告)日：2015-12-03
申请号：US14675230
申请日：2015-03-31
Applicant: STMICROELECTRONICS S.R.L.
IPC: B81B7/00
CPC classification number: B81B7/008 , B81B3/00 , B81B7/04 , B81B2201/0257 , B81B2207/03 , B81B2207/053 , H04R3/007 , H04R3/12 , H04R19/005 , H04R2201/003
Abstract: A system for driving a MEMS array having a number of MEMS structures, each defining at least one row terminal and one column terminal, envisages: a number of row driving stages, each for supplying row-biasing signals to the row terminal of each MEMS structure associated to a respective row; a number of column driving stages, each for supplying column-biasing signals to the column terminal of each MEMS structure associated to a respective column; and a control unit, for supplying row-address signals to the row driving stages for generation of the row-biasing signals and for supplying column-address signals to the column driving stages for generation of the column-biasing signals. The control unit further supplies row-deactivation and/or column-deactivation signals to one or more of the row and column driving stages, for causing deactivation of one or more rows and/or columns of the MEMS array.
Abstract translation: 用于驱动具有多个MEMS结构的MEMS阵列的系统，每个MEMS结构限定至少一个行端子和一个列端子，设想：多个行驱动级，每个用于向每个MEMS结构的行端子提供行偏置信号 相关联的行; 多个列驱动级，每个列驱动级用于向与各列相关联的每个MEMS结构的列端子提供列偏置信号; 以及控制单元，用于将行地址信号提供到行驱动级，用于产生行偏置信号，并将列地址信号提供给列驱动级，以产生列偏置信号。 控制单元还向行驱动级和列驱动级中的一个或多个驱动级提供行去激活和/或列停用信号，以使MEMS阵列的一个或多个行和/或列的去激活。
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公开(公告)号：US20250015708A1
公开(公告)日：2025-01-09
申请号：US18218750
申请日：2023-07-06
Applicant: STMicroelectronics S.r.l. , Politecnico Di Milano
Inventor： Lorenzo CREMONESI , Paolo MELILLO , Alessandro GASPARINI , Massimo GHIONI , Salvatore LEVANTINO
Abstract: Disclosed herein is a DC-DC converter, including a high-side power switch coupled between an input voltage and a switched node and a low-side power switch coupled between the switched node and ground. An inductor is coupled between the switched node and an output node. An output capacitor is coupled between the output node and ground. A control circuit is configured to operate the high-side power switch in a constant charge mode of operation to vary on-time of the high-side power switch to maintain a constant amount of charge being transferred to the output capacitor during each charging cycle, independent of variation of the input voltage.
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公开(公告)号：US20210384830A1
公开(公告)日：2021-12-09
申请号：US17335523
申请日：2021-06-01
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alberto CATTANI , Alessandro GASPARINI
Abstract: A control circuit for controlling switching operation of a switching stage of a converter includes a phase detector circuit that generates a pulse-width modulated (PWM) signal in response to a phase comparison of two clock signals. A first clock signal has a frequency determined as a function of a first feedback signal proportional to converter output voltage. A first transconductance amplifier generates a first current indicative of a difference between a reference voltage and the first feedback signal, and a second transconductance amplifier generates a second current indicative of a difference between the reference voltage and a second feedback signal proportional to a derivative of the converter output voltage. A delay line introduces a delay in the first clock signal that is dependent on the first and second currents as well as a compensation current dependent on a selected operational mode of the converter.
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公开(公告)号：US20210184576A1
公开(公告)日：2021-06-17
申请号：US17117847
申请日：2020-12-10
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto CATTANI , Alessandro GASPARINI
Abstract: First and second n-channel FETs are connected in series between first and second terminals with an intermediate switching node. First and second driver circuits drive gates of the first and second n-channel FETs, respectively, in response to drive signals. The first driver circuit does not implement slew-rate control. A first resistor and capacitor are connected in series between the output of the first driver circuit and an intermediate node. A first electronic switch is connected between the intermediate node and the first terminal. A second electronic switch is connected between the intermediate node and the gate terminal of the first n-channel FET. A second resistor and a third electronic switch are connected in series between the gate terminal of the first n-channel FET and the switching node. A control circuit generates the drive signals and a first, second and third control signal for the first, second and third electronic switch.
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Patent Agency Ranking
公开(公告)号：US20210013808A1
公开(公告)日：2021-01-14
申请号：US16924410
申请日：2020-07-09
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto CATTANI , Alessandro GASPARINI
Abstract: First and second FETs of a half-bridge are series connected between first and second terminals and are gate driven, respectively, by first and second drivers. An inductance is connected to the intermediate node of the half-bridge. Power supply for the second driver circuit is a supply voltage generated by a voltage regulator as a function of the voltage between the first and the second terminal. Power supply for the first driver circuit is a supply voltage generated by a bootstrap capacitor having a first terminal connected via a first switch to receive the supply voltage output from the voltage regulator and a second terminal connected to the intermediate node. The first terminal of the bootstrap capacitor is further connected by a second switch to receive a second supply voltage. A control circuit generates control signals for the first and second driver circuits and the first and second switches.
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7.发明申请公开(公告)号：US20160268887A1
公开(公告)日：2016-09-15
申请号：US15163394
申请日：2016-05-24
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Stefano RAMORINI , Alessandro GASPARINI , Alberto CATTANI
Abstract: An electrical-energy harvesting system envisages a transducer for converting energy from an environmental energy source into a transduced signal, an electrical energy harvesting interface for receiving the transduced signal and for supplying a harvesting signal, and an energy storage element coupled to the electrical energy harvesting interface for receiving the harvesting signal. The electrical-energy harvesting system also includes a voltage converter connected to the electrical energy harvesting interface for generating a regulated voltage. The harvesting interface samples an open-circuit voltage value of the transduced signal, generates an optimized voltage value starting from the open-circuit voltage value, and generates an upper threshold voltage and a lower threshold voltage on the basis of the optimized voltage value. The harvesting interface controls the voltage converter in switching mode so that the harvesting signal has a value between the upper and lower threshold voltages in at least one operating condition.
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公开(公告)号：US20240128871A1
公开(公告)日：2024-04-18
申请号：US18376277
申请日：2023-10-03
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alessandro GASPARINI , Paolo MELILLO , Salvatore LEVANTINO , Massimo GHIONI
Abstract: A boost DC-DC converter includes a switching network, coupled to an inductor, controlled by a PWM driving signal. A control loop receives a voltage output and provides the PWM driving signal. The control loop generates an error signal as a function of a difference between voltage output voltage and a reference, with the PWM driving signal generated based on the error signal. A low pass filter circuit within the control loop receives the PWM driving signal and provides at least one filtered signal. An adder node of the control loop receives the at least one filtered signal from the low pass filter circuit for addition to the at least one filtered signal. The PWM driving signal is generated as a function of a sum of the filtered signal and the error signal.
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公开(公告)号：US20220166315A1
公开(公告)日：2022-05-26
申请号：US17533338
申请日：2021-11-23
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI , Alessandro GASPARINI , Alberto CATTANI
IPC: H02M3/07
Abstract: Charge pump stages are coupled between flying capacitor pairs and arranged in a cascaded between a bottom voltage line and an output voltage line. Gain stages apply pump phase signals having a certain amplitude to the charge pump stages via the flying capacitors. A feedback signal path from the output voltage line to the bottom voltage line applies a feedback control signal to the bottom voltage line. Power supply for the gain stages is provided by a voltage of the feedback control signal in order to control the amplitude of the pump phase signals. An asynchronous logic circuit generates the switching drive signals for the gain stages with a certain switching frequency which is a function of a logic supply voltage derived from the voltage of the feedback control signal.
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公开(公告)号：US20210074835A1
公开(公告)日：2021-03-11
申请号：US16561670
申请日：2019-09-05
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto CATTANI , Alessandro GASPARINI
IPC: H01L29/739 , H02M1/32 , H02M3/158
Abstract: A power MOS stage includes a first power MOS device and a second power MOS devices connected in parallel between a first node and a second node, the first power MOS device having a first voltage rating and the second power MOS device having a second voltage rating that is lower than the first voltage rating. A driver circuit is configured to drive control nodes of the first and second power MOS devices in a sequential manner when actuating the power MOS stage by actuating the first power MOS device before actuating the second power MOS device. The control nodes of the first and second power MOS devices are further driven in a sequential manner when deactuating the power MOS stage by deactuating the second power MOS device before deactuating the first power MOS device.
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