Invention Application
- Patent Title: ELECTRICAL OVERSTRESS PROTECTION FOR ELECTRONIC SYSTEMS SUBJECT TO ELECTROMAGNETIC COMPATIBILITY FAULT CONDITIONS
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Application No.: US16719490Application Date: 2019-12-18
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Publication No.: US20210098614A1Publication Date: 2021-04-01
- Inventor: Javier A. Salcedo , Linfeng He
- Applicant: Analog Devices, Inc.
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Main IPC: H01L29/74
- IPC: H01L29/74 ; H01L27/02

Abstract:
Electrical overstress protection for electronic systems subject to electromagnetic compatibility fault conditions are provided herein. In certain implementations, a stacked thyristor protection structure with a high holding voltage includes a protection device having a trigger voltage and a holding voltage. A trigger voltage of the stacked thyristor protection structure is substantially equal to the trigger voltage of the protection device. The stacked thyristor protection structure further includes at least one resistive thyristor electrically connected to the protection device and operable to increase a holding voltage of the stacked thyristor protection structure relative to the holding voltage of the protection device. The at least one resistive thyristor comprising a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and a conductor connecting a collector of the PNP bipolar transistor to a collector of the NPN bipolar transistor.
Public/Granted literature
Information query
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