公开(公告)号：US20210344336A1

公开(公告)日：2021-11-04

申请号：US16863830

申请日：2020-04-30

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Jonathan G. Pfeifer

IPC: H03K17/081 ,  H01L29/74 ,  H01L29/78 ,  H01L27/02

Abstract: Fin field-effect transistor (FinFET) thyristors for protecting high-speed communication interfaces are provided. In certain embodiments herein, high voltage tolerant FinFET thyristors are provided for handling high stress current and high RF power handling capability while providing low capacitance to allow wide bandwidth operation. Thus, the FinFET thyristors can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, while addressing tight radio frequency design window and robustness. In certain implementations, the FinFET thyristors include a first thyristor, a FinFET triggering circuitry and a second thyristor that serves to provide bidirectional blocking voltage and overstress protection. The FinFET triggering circuitry also enhances turn-on speed of the thyristor and/or reduces total on-state resistance.

公开(公告)号：US20200286889A1

公开(公告)日：2020-09-10

申请号：US16294431

申请日：2019-03-06

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Andrew Lewine

IPC: H01L27/092 ,  H01L29/87 ,  H01L27/02 ,  H01C7/12

Abstract: Electrical overstress protection for high speed applications, such as integrated multiple subsystem communications, is provided. In certain embodiments, a semiconductor die with distributed and configurable electrical overstress protection is provided. The semiconductor die includes signal pads, a core circuit electrically connected to the signal pads, and a configurable overstress protection array operable to protect the core circuit from electrical overstress at the signal pads. The configurable overstress protection array includes a plurality of segmented overstress protection devices of two or more different device types, and both a number of selected overstress protection devices and a device type of the selected overstress protection devices is programmable. The subsystems configurations are enabled in FinFET technology. Such configurable overstress protection arrays can be distributed across the die to protect not only core circuit sub-systems at the die pads, but also between internal sub-system communication interfaces operating in different power domains.

公开(公告)号：US11595036B2

公开(公告)日：2023-02-28

申请号：US16863830

申请日：2020-04-30

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Jonathan G. Pfeifer

IPC: H01L29/74 ,  H01L29/78 ,  H01L27/02 ,  H03K17/081

Abstract: Fin field-effect transistor (FinFET) thyristors for protecting high-speed communication interfaces are provided. In certain embodiments herein, high voltage tolerant FinFET thyristors are provided for handling high stress current and high RF power handling capability while providing low capacitance to allow wide bandwidth operation. Thus, the FinFET thyristors can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, while addressing tight radio frequency design window and robustness. In certain implementations, the FinFET thyristors include a first thyristor, a FinFET triggering circuitry and a second thyristor that serves to provide bidirectional blocking voltage and overstress protection. The FinFET triggering circuitry also enhances turn-on speed of the thyristor and/or reduces total on-state resistance.

公开(公告)号：US11462535B2

公开(公告)日：2022-10-04

申请号：US17306563

申请日：2021-05-03

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Andrew Lewine

IPC: H01L27/092 ,  H01C7/12 ,  H01L27/02 ,  H01L29/87

Abstract: Electrical overstress protection for high speed applications is provided. In certain embodiments, a method of distributed and customizable electrical overstress protection for a semiconductor die is provided. The method includes configuring a heterogeneous overstress protection array that includes a customizable forward protection circuit electrically connected between a power high pad, a power low pad, and a signal pad and distributed across the semiconductor die, including selecting a number of segmented overstress protection devices from a plurality of available overstress protection devices of the customizable protection circuit. The method also includes choosing a device type of the selected segmented overstress protection devices from amongst two or more different device types providing complementary protection characteristics and protecting a core circuit from electrical overstress using the selected segmented overstress protection devices, the core circuit electrically connected to at least the signal pad, the power high pad, and the power low pad.

公开(公告)号：US20130222961A1

公开(公告)日：2013-08-29

申请号：US13863155

申请日：2013-04-15

Applicant: Analog Devices, Inc.

Inventor： Srivatsan Parthasarathy ,  Javier A. Salcedo

IPC: H02H3/22

CPC classification number: H02H3/22 ,  H01L27/0259 ,  H02H9/046

Abstract: Apparatuses and methods for providing transient electrical event protection are disclosed. In one embodiment, an apparatus comprises a detection and timing circuit, a current amplification circuit, and a clamping circuit. The detection and timing circuit is configured to detect a presence or absence of a transient electrical event at a first node, and to generate a first current for a first duration upon detection of the transient electrical event. The current amplification circuit is configured to receive the first current from the detection and timing circuit and to amplify the first current to generate a second current. The clamping circuit is electrically connected between the first node and a second node and receives the second current for activation. The clamping circuit is configured to activate a low impedance path between the first and second nodes in response to the second current, and to otherwise deactivate the low impedance path.

Abstract translation: 公开了用于提供瞬时电气事件保护的装置和方法。 在一个实施例中，一种装置包括检测和定时电路，电流放大电路和钳位电路。 检测和定时电路被配置为检测在第一节点处的瞬时电事件的存在或不存在，并且在检测到瞬态电事件时产生第一持续时间的第一电流。 电流放大电路被配置为从检测和定时电路接收第一电流并且放大第一电流以产生第二电流。 钳位电路电连接在第一节点和第二节点之间，并接收用于激活的第二电流。 钳位电路被配置为响应于第二电流来激活第一和第二节点之间的低阻抗路径，并且否则去激活低阻抗路径。

公开(公告)号：US20230163757A1

公开(公告)日：2023-05-25

申请号：US18157550

申请日：2023-01-20

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Jonathan G. Pfeifer

IPC: H03K17/081 ,  H01L27/02 ,  H01L29/78 ,  H01L29/74

CPC classification number: H03K17/08108 ,  H01L27/0262 ,  H01L29/785 ,  H01L29/742

Abstract: Fin field-effect transistor (FinFET) thyristors for protecting high-speed communication interfaces are provided. In certain embodiments herein, high voltage tolerant FinFET thyristors are provided for handling high stress current and high RF power handling capability while providing low capacitance to allow wide bandwidth operation. Thus, the FinFET thyristors can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, while addressing tight radio frequency design window and robustness. In certain implementations, the FinFET thyristors include a first thyristor, a FinFET triggering circuitry and a second thyristor that serves to provide bidirectional blocking voltage and overstress protection. The FinFET triggering circuitry also enhances turn-on speed of the thyristor and/or reduces total on-state resistance.

公开(公告)号：US20210098614A1

公开(公告)日：2021-04-01

申请号：US16719490

申请日：2019-12-18

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Linfeng He

IPC: H01L29/74 ,  H01L27/02

Abstract: Electrical overstress protection for electronic systems subject to electromagnetic compatibility fault conditions are provided herein. In certain implementations, a stacked thyristor protection structure with a high holding voltage includes a protection device having a trigger voltage and a holding voltage. A trigger voltage of the stacked thyristor protection structure is substantially equal to the trigger voltage of the protection device. The stacked thyristor protection structure further includes at least one resistive thyristor electrically connected to the protection device and operable to increase a holding voltage of the stacked thyristor protection structure relative to the holding voltage of the protection device. The at least one resistive thyristor comprising a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and a conductor connecting a collector of the PNP bipolar transistor to a collector of the NPN bipolar transistor.

公开(公告)号：US20130330884A1

公开(公告)日：2013-12-12

申请号：US13966938

申请日：2013-08-14

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  David Hall Whitney

IPC: H01L21/8222

CPC classification number: H01L21/8222 ,  H01L27/0262

Abstract: Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.

Abstract translation: 提供了在高应力操作条件下进行电子电路保护的装置和方法。 在一个实施例中，一种装置包括具有第一p阱，邻近第一p阱的第二p阱和分离第一和第二p阱的n型区的衬底。 n型有源区域在第一p阱上方，p型有源区域超过第二个p阱。 n型和p型有源区分别电连接到高反向阻断电压（HRBV）器件的阴极和阳极。 n型有源区，第一p阱和n型区用作NPN双极晶体管，第二p阱，n型区和第一p阱用作PNP双极晶体管。 NPN双极晶体管定义了HRBV器件的相对低的正向触发电压，PNP双极晶体管限定了HRBV器件的相对高的反向击穿电压。

公开(公告)号：US11362203B2

公开(公告)日：2022-06-14

申请号：US16719490

申请日：2019-12-18

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Linfeng He

IPC: H01L27/02 ,  H01L29/74 ,  H01L27/08 ,  H01L27/12 ,  H01L29/08

Abstract: Electrical overstress protection for electronic systems subject to electromagnetic compatibility fault conditions are provided herein. In certain implementations, a stacked thyristor protection structure with a high holding voltage includes a protection device having a trigger voltage and a holding voltage. A trigger voltage of the stacked thyristor protection structure is substantially equal to the trigger voltage of the protection device. The stacked thyristor protection structure further includes at least one resistive thyristor electrically connected to the protection device and operable to increase a holding voltage of the stacked thyristor protection structure relative to the holding voltage of the protection device. The at least one resistive thyristor comprising a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and a conductor connecting a collector of the PNP bipolar transistor to a collector of the NPN bipolar transistor.

公开(公告)号：US11342323B2

公开(公告)日：2022-05-24

申请号：US16700989

申请日：2019-12-02

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Linfeng He

IPC: H01L27/02 ,  H02H9/04 ,  H01L29/74 ,  H01L29/08 ,  H01L29/417 ,  H01L29/40

Abstract: A semiconductor die with high-voltage tolerant electrical overstress circuit architecture is disclosed. One embodiment of the semiconductor die includes a signal pad, a ground pad, a core circuit electrically connected to the signal pad, and a stacked thyristor protection device. The stacked thyristor includes a first thyristor and a resistive thyristor electrically connected in a stack between the signal pad and the ground pad, which enhances the holding voltage of the circuit relatively to an implementation with only the thyristor. Further, the resistive thyristor includes a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and an electrical connection between a collector of the PNP bipolar transistor and a collector of the NPN bipolar transistor. This allows the resistive thyristor to exhibit both thyristor characteristics and resistive characteristics based on a level of current flow.