- 专利标题: CIRCUIT ARRANGEMENT WITH CLOCK SHARING, AND CORRESPONDING METHOD
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申请号: US17035074申请日: 2020-09-28
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公开(公告)号: US20210111712A1公开(公告)日: 2021-04-15
- 发明人: Liliana Arcidiacono , Santi Carlo Adamo
- 申请人: STMicroelectronics S.r.l.
- 申请人地址: IT Agrate Brianza
- 专利权人: STMicroelectronics S.r.l.
- 当前专利权人: STMicroelectronics S.r.l.
- 当前专利权人地址: IT Agrate Brianza
- 优先权: IT102019000018587 20191011
- 主分类号: H03K5/15
- IPC分类号: H03K5/15
摘要:
In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.
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