公开(公告)号：US11115013B2

公开(公告)日：2021-09-07

申请号：US17035074

申请日：2020-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： Liliana Arcidiacono ,  Santi Carlo Adamo

IPC: H03K5/00 ,  H03K5/15

Abstract: In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.

公开(公告)号：US09160186B2

公开(公告)日：2015-10-13

申请号：US13774232

申请日：2013-02-22

Applicant: STMicroelectronics S.r.l.

Inventor： Agatino Antonino Alessandro ,  Giuliana Demilato ,  Liliana Arcidiacono ,  Santi Carlo Adamo

IPC: H02J7/00

CPC classification number: H02J7/0052 ,  H02J7/0009 ,  H02J7/0022 ,  H02J7/0024 ,  H02J7/0031 ,  H02J7/0068 ,  H02J7/0077 ,  H02J7/008 ,  H02J2007/0039 ,  H02J2007/004 ,  H02J2007/0062

Abstract: A battery charger includes an input supply terminal configured to receive a supply signal, a battery terminal configured to be connected to a battery and at least one output terminal, a switch arranged in the electrical path between the battery terminal and at least one output terminal, an element configured to store an information representative of an alarm condition of the battery and to open the switch when the alarm condition occurs, with the supply signal being absent and the battery supplying the at least one output terminal, and to close the switch when the supply signal is received at the input supply terminal.

Abstract translation: 电池充电器包括被配置为接收电源信号的输入电源端子，被配置为连接到电池和至少一个输出端子的电池端子，布置在电池端子和至少一个输出端子之间的电气路径中的开关， 被配置为存储表示电池的警报状况的信息的元件，并且当所述警报状况发生时打开所述开关，所述电源信号不存在，并且所述电池提供所述至少一个输出端子，并且当所述电源提供所述至少一个输出端子时关闭所述开关 在输入电源端子接收电源信号。

公开(公告)号：US20130229146A1

公开(公告)日：2013-09-05

申请号：US13774324

申请日：2013-02-22

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Giuliana Demilato ,  Agatino Antonino Alessandro ,  Santi Carlo Adamo ,  Liliana Arcidiacono

IPC: H02J7/00

CPC classification number: H02J7/0029 ,  H02J7/0009 ,  H02J7/0022 ,  H02J7/0024 ,  H02J7/0031 ,  H02J7/0052 ,  H02J7/0068 ,  H02J7/0077 ,  H02J7/008 ,  H02J9/06 ,  H02J2007/0062

Abstract: A battery charger which includes an input supply terminal configured to receive a supply signal, a battery terminal configured to be connected to a battery, at least one output terminal and an electrical path between the battery terminal and the output terminal, at least one device for the detection of one alarm condition of the battery or the battery charger. The battery charger includes circuitry configured to enable the at least one detection device at timing intervals when the battery supplies the at least one output terminal.

Abstract translation: 一种电池充电器，包括被配置为接收电源信号的输入电源端子，被配置为连接到电池的电池端子，至少一个输出端子和电池端子与输出端子之间的电路径，至少一个装置， 检测电池或电池充电器的一个报警状态。 电池充电器包括被配置为当电池提供至少一个输出端子的定时间隔使能至少一个检测装置的电路。

公开(公告)号：US11431330B2

公开(公告)日：2022-08-30

申请号：US17393916

申请日：2021-08-04

Applicant: STMicroelectronics S.r.l.

Inventor： Liliana Arcidiacono ,  Santi Carlo Adamo

IPC: H03K5/04 ,  H03K5/15

Abstract: In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.

公开(公告)号：US09184606B2

公开(公告)日：2015-11-10

申请号：US13774324

申请日：2013-02-22

Applicant: STMicroelectronics S.r.l.

Inventor： Giuliana Demilato ,  Agatino Antonino Alessandro ,  Santi Carlo Adamo ,  Liliana Arcidiacono

IPC: H02J7/00 ,  H02J9/06

CPC classification number: H02J7/0029 ,  H02J7/0009 ,  H02J7/0022 ,  H02J7/0024 ,  H02J7/0031 ,  H02J7/0052 ,  H02J7/0068 ,  H02J7/0077 ,  H02J7/008 ,  H02J9/06 ,  H02J2007/0062

Abstract: A battery charger which includes an input supply terminal configured to receive a supply signal, a battery terminal configured to be connected to a battery, at least one output terminal and an electrical path between the battery terminal and the output terminal, at least one device for the detection of one alarm condition of the battery or the battery charger. The battery charger includes circuitry configured to enable the at least one detection device at timing intervals when the battery supplies the at least one output terminal.

Abstract translation: 一种电池充电器，包括被配置为接收电源信号的输入电源端子，被配置为连接到电池的电池端子，至少一个输出端子和电池端子与输出端子之间的电路径，至少一个装置， 检测电池或电池充电器的一个报警状态。 电池充电器包括被配置为当电池提供至少一个输出端子的定时间隔使能至少一个检测装置的电路。

公开(公告)号：US11626880B2

公开(公告)日：2023-04-11

申请号：US17450711

申请日：2021-10-13

Applicant: STMicroelectronics S.r.l.

Inventor： Liliana Arcidiacono ,  Alessandro Nicolosi ,  Valeria Bottarel

IPC: H03K19/17736 ,  H03K19/08

Abstract: A circuit receives an input signal having a first level and a second level. A logic circuit includes a finite state machine circuit, an edge detector circuit, and a timer circuit. The finite state machine circuit is configured to set a mode of operation of the circuit. The edge detector circuit is configured to detect a transition between the first and second level. The timer circuit is configured to determine whether the first or second level is maintained over an interval, which starts from a transition detected by the edge detector circuit. The finite state machine circuit is configured to change the mode of operation based on the timer circuit determining that the first or second level has been maintained over the interval.

公开(公告)号：US20220149844A1

公开(公告)日：2022-05-12

申请号：US17450711

申请日：2021-10-13

Applicant: STMicroelectronics S.r.l.

Inventor： Liliana Arcidiacono ,  Alessandro Nicolosi ,  Valeria Bottarel

IPC: H03K19/17736 ,  H03K19/08

Abstract: A circuit receives an input signal having a first level and a second level. A logic circuit includes a finite state machine circuit, an edge detector circuit, and a timer circuit. The finite state machine circuit is configured to set a mode of operation of the circuit. The edge detector circuit is configured to detect a transition between the first and second level. The timer circuit is configured to determine whether the first or second level is maintained over an interval, which starts from a transition detected by the edge detector circuit. The finite state machine circuit is configured to change the mode of operation based on the timer circuit determining that the first or second level has been maintained over the interval.

公开(公告)号：US20210367589A1

公开(公告)日：2021-11-25

申请号：US17393916

申请日：2021-08-04

Applicant: STMicroelectronics S.r.l.

Inventor： Liliana Arcidiacono ,  Santi Carlo Adamo

IPC: H03K5/15

Abstract: In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.

公开(公告)号：US20210111712A1

公开(公告)日：2021-04-15

申请号：US17035074

申请日：2020-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： Liliana Arcidiacono ,  Santi Carlo Adamo

IPC: H03K5/15

Abstract: In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.

公开(公告)号：US09735599B2

公开(公告)日：2017-08-15

申请号：US14725506

申请日：2015-05-29

Applicant: STMicroelectronics S.r.l.

Inventor： Agatino Antonino Alessandro ,  Carmelo Alberto Santagati ,  Liliana Arcidiacono ,  Francesco Pirozzi

IPC: H01M10/44 ,  H01M10/46 ,  H02J7/00 ,  G01R31/36

CPC classification number: H02J7/0052 ,  G01R31/3655 ,  H01M10/44

Abstract: A battery charger includes an input supply terminal configured to receive a supply signal and a battery terminal configured to be connected to a battery. A supply switching circuit is arranged between the battery terminal and the input supply terminal. A control device generates a control signal to control operation of the supply switching circuit. A fuel gauge device provide a digital estimation of a voltage signal across the battery. A correction device modifies the control signal in response to the digital estimation of the voltage signal across the battery if that digital estimation is outside of a value range between two thresholds.