- 专利标题: DYNAMIC INTEGRATION TIME ADJUSTMENT OF A CLOCKED DATA SAMPLER USING A STATIC ANALOG CALIBRATION CIRCUIT
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申请号: US17347589申请日: 2021-06-15
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公开(公告)号: US20210305993A1公开(公告)日: 2021-09-30
- 发明人: Kiarash Gharibdoust , Armin Tajalli , Pavan Kumar Jampani , Ali Hormati
- 申请人: Kandou Labs SA
- 申请人地址: CH Lausanne
- 专利权人: Kandou Labs SA
- 当前专利权人: Kandou Labs SA
- 当前专利权人地址: CH Lausanne
- 主分类号: H03M1/12
- IPC分类号: H03M1/12 ; H03M1/36 ; H03M1/10 ; H03M1/06
摘要:
Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.
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