Invention Application
- Patent Title: SYSTEMS, APPARATUS, AND METHODS TO DEBUG ACCELERATOR HARDWARE
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Application No.: US17483521Application Date: 2021-09-23
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Publication No.: US20220012164A1Publication Date: 2022-01-13
- Inventor: Martin-Thomas Grymel , David Bernard , Martin Power , Niall Hanrahan , Kevin Brady
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F11/36
- IPC: G06F11/36 ; G06F11/30 ; G06F11/277 ; G06N3/04

Abstract:
Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.
Public/Granted literature
- US11829279B2 Systems, apparatus, and methods to debug accelerator hardware Public/Granted day:2023-11-28
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