Invention Application
- Patent Title: MEMORY SUB-SYSTEM LOGICAL BLOCK ADDRESS REMAPPING
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Application No.: US17027895Application Date: 2020-09-22
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Publication No.: US20220091975A1Publication Date: 2022-03-24
- Inventor: Kishore K. Muchherla , Vamsi Pavan Rayaprolu , Karl D. Schuh , Jiangang Wu , Gil Golov
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G06F12/0882 ; G06F12/0811 ; G06F12/0873 ; G06F11/30
Abstract:
A system includes a memory device and a processing device coupled to the memory device. The processing device can determine a data rate from a first sensor and a data rate from a second sensor. The processing device can write a first set of data received from the first sensor at a first logical block address (LBA) in the memory device. The processing device can write a second set of data received from the second sensor and subsequent to the first set of data at a second LBA in the memory device. The processing device can remap the first LBA and the second LBA to be logically sequential LBAs. The second LBA can be associated with an offset from the first LBA and the offset can correspond to a data rate of the first sensor.
Public/Granted literature
- US11416388B2 Memory sub-system logical block address remapping Public/Granted day:2022-08-16
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