公开(公告)号：US12164804B2

公开(公告)日：2024-12-10

申请号：US17552237

申请日：2021-12-15

Applicant: Micron Technology, Inc.

Inventor： Karl D. Schuh ,  Jiangang Wu ,  Kishore K. Muchherla ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device can assign each of a plurality of superblocks to one of a plurality of groups. The processing device can monitor an order that each of the groups have been written to. The processing device can write data to a first block of a first superblock of a first of the plurality of groups.

公开(公告)号：US12148484B2

公开(公告)日：2024-11-19

申请号：US17992035

申请日：2022-11-22

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Karl D. Schuh ,  Jeffrey S. McNeil, Jr. ,  Kishore K Muchherla ,  Ashutosh Malshe ,  Jiangang Wu

IPC: G11C16/34 ,  G06F12/02 ,  G11C16/14 ,  G11C16/26 ,  G11C29/10

Abstract: A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.

公开(公告)号：US12001340B2

公开(公告)日：2024-06-04

申请号：US18124447

申请日：2023-03-21

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Qisong Lin ,  Jung Sheng Hoei ,  Yunqiu Wan ,  Ashutosh Malshe ,  Peng-Cheng Chen

IPC: G06F11/00 ,  G06F11/14 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/0882 ,  G06F12/0891 ,  G06F13/16 ,  G11C16/06

CPC classification number: G06F12/0891 ,  G06F11/14 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0882 ,  G06F13/1668 ,  G11C16/06

Abstract: Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.

公开(公告)号：US11783901B2

公开(公告)日：2023-10-10

申请号：US17880980

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Karl D. Schuh ,  Jiangang Wu ,  Devin M. Batutis ,  Xiangang Luo

IPC: G11C16/26 ,  G11C16/34 ,  G06F3/06 ,  G06F11/07 ,  G11C16/04

CPC classification number: G11C16/34 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/076 ,  G06F11/0727 ,  G06F11/0793 ,  G11C16/26 ,  G11C16/0483

Abstract: A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.

公开(公告)号：US11748013B2

公开(公告)日：2023-09-05

申请号：US17949977

申请日：2022-09-21

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Jiangang Wu ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Peter Feeley ,  Karl D. Schuh

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/04

CPC classification number: G06F3/064 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G11C16/10 ,  G11C16/0483

Abstract: An initial value of a power cycle count associated with the memory device is identified. The power cycle count is incremented responsive to detecting a powering up of the memory device. Responsive to programming a block residing in the memory device, the block is associated with a current block family associated with the memory device. A currently value of the power cycle count is determined. Responsive to determining that a difference between the initial value of the power cycle count and the current value of the power cycle count satisfies a predefined condition, the current block family is closed.

公开(公告)号：US11676664B2

公开(公告)日：2023-06-13

申请号：US17883538

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath K. Ratnam ,  Shane Nowell ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Karl D. Schuh ,  Peter Feeley ,  Jiangang Wu

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/20 ,  G11C16/32 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/102 ,  G11C16/20 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3495

Abstract: A processing device of a memory sub-system is configured to detect a power on event that is associated with a memory device and indicates that power has been restored to the memory device; estimate a duration of a power off state preceding the power on event associated with the memory device; and update voltage bin assignments of a plurality of blocks associated with the memory device based on the duration of the power off state.

公开(公告)号：US20230122275A1

公开(公告)日：2023-04-20

申请号：US18083992

申请日：2022-12-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Sivagnanam Parthasarathy ,  Xiangang Luo ,  Peter Feeley ,  Devin M. Batutis ,  Jiangang Wu ,  Sampath K. Ratnam ,  Shane Nowell ,  Karl D. Schuh

IPC: G11C29/50 ,  G06F12/02 ,  G11C16/26 ,  G11C29/02 ,  G11C7/10

Abstract: A method includes initiating a voltage calibration scan with respect to a block of a memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin, measuring a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin, determining whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets, and in response to determining that the value is less than the current value, designating the second bin as the current bin.

公开(公告)号：US20230085178A1

公开(公告)日：2023-03-16

申请号：US17992035

申请日：2022-11-22

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Karl D. Schuh ,  Jeffrey S. McNeil Jr. ,  Kishore K. Muchherla ,  Ashutosh Malshe ,  Jiangang Wu

IPC: G11C16/34 ,  G11C16/14 ,  G11C29/10 ,  G06F12/02 ,  G11C16/26

Abstract: A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.

公开(公告)号：US20230019189A1

公开(公告)日：2023-01-19

申请号：US17952927

申请日：2022-09-26

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Jung Sheng Hoei ,  Qisong Lin ,  Kishore Kumar Muchherla

IPC: G06F3/06

Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.

公开(公告)号：US11520502B2

公开(公告)日：2022-12-06

申请号：US16731936

申请日：2019-12-31

Applicant: Micron Technology, Inc.

Inventor： Yun Li ,  James P. Crowley ,  Jiangang Wu ,  Peng Xu

IPC: G06F3/06

Abstract: Methods, systems, and devices for performance control for a memory sub-system are described. A memory sub-system can monitor a backend for writing data to a memory device. The memory sub-system can determine that the bandwidth of the backend satisfies one or more performance criteria that are based on performance between the memory sub-system and a host system. In some embodiments, the memory sub-system can allocate a quantity of slots of a buffer to a frontend of the memory sub-system based on determining that the bandwidth of the backend satisfies the one or more performance criteria. Slots of the buffer can be configured to receive data from the frontend for writing to the memory device by the backend.