Provided is a manufacturing method of a memory device, including: forming a stacked layer on a substrate; patterning the stacked layer to form a plurality of openings in the stacked layer; forming a spacer on a sidewall of the openings; performing a first etching process by using the spacer as a mask to form a plurality of stack structures, wherein the spacer is embedded in the stack structures, such that a width of an upper portion of the stack structures is less than a width of a lower portion thereof; forming a dielectric layer on the stack structures and the spacer; and respectively forming a plurality of contact plugs on the substrate between the stack structures.