公开(公告)号：US20220123007A1

公开(公告)日：2022-04-21

申请号：US17567850

申请日：2022-01-03

Applicant: Winbond Electronics Corp.

Inventor： Jian-Ting Chen ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC: H01L27/11556 ,  H01L29/788 ,  H01L29/66 ,  H01L21/8234

Abstract: Provided is a manufacturing method of a memory device, including: forming a stacked layer on a substrate; patterning the stacked layer to form a plurality of openings in the stacked layer; forming a spacer on a sidewall of the openings; performing a first etching process by using the spacer as a mask to form a plurality of stack structures, wherein the spacer is embedded in the stack structures, such that a width of an upper portion of the stack structures is less than a width of a lower portion thereof; forming a dielectric layer on the stack structures and the spacer; and respectively forming a plurality of contact plugs on the substrate between the stack structures.

公开(公告)号：US11257833B2

公开(公告)日：2022-02-22

申请号：US16568297

申请日：2019-09-12

Applicant: Winbond Electronics Corp.

Inventor： Jian-Ting Chen ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC: H01L29/423 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/66 ,  H01L21/8234

Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a spacer, a dielectric layer, and a plurality of contact plugs. The stack structures are disposed on the substrate. The spacer is embedded in the stack structures, so that a width of an upper portion of the stack structures is less than a width of a lower portion thereof. The dielectric layer conformally covers the stack structures and the spacer. The contact plugs are respectively disposed on the substrate between the stack structures.

公开(公告)号：US20200273871A1

公开(公告)日：2020-08-27

申请号：US16568297

申请日：2019-09-12

Applicant: Winbond Electronics Corp.

Inventor： Jian-Ting Chen ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC: H01L27/11556 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/788

Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a spacer, a dielectric layer, and a plurality of contact plugs. The stack structures are disposed on the substrate. The spacer is embedded in the stack structures, so that a width of an upper portion of the stack structures is less than a width of a lower portion thereof. The dielectric layer conformally covers the stack structures and the spacer. The contact plugs are respectively disposed on the substrate between the stack structures.

公开(公告)号：US11805644B2

公开(公告)日：2023-10-31

申请号：US17567850

申请日：2022-01-03

Applicant: Winbond Electronics Corp.

Inventor： Jian-Ting Chen ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC: H01L27/11556 ,  H10B41/27 ,  H01L29/788 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H10B41/27 ,  H01L21/823437 ,  H01L29/66825 ,  H01L29/788

Abstract: Provided is a manufacturing method of a memory device, including: forming a stacked layer on a substrate; patterning the stacked layer to form a plurality of openings in the stacked layer; forming a spacer on a sidewall of the openings; performing a first etching process by using the spacer as a mask to form a plurality of stack structures, wherein the spacer is embedded in the stack structures, such that a width of an upper portion of the stack structures is less than a width of a lower portion thereof; forming a dielectric layer on the stack structures and the spacer; and respectively forming a plurality of contact plugs on the substrate between the stack structures.

公开(公告)号：US20230017264A1

公开(公告)日：2023-01-19

申请号：US17375000

申请日：2021-07-14

Applicant: Winbond Electronics Corp.

Inventor： Yu-Lung Wang ,  Yao-Ting Tsai ,  Jian-Ting Chen ,  Yuan-Huang Wei

IPC: H01L29/788 ,  H01L27/11521 ,  H01L29/417 ,  H01L21/311 ,  H01L29/66 ,  H01L29/40

Abstract: Provided is a semiconductor device including a substrate, multiple first gate structures, and a protective structure. The substrate includes a first region and a second region. The first gate structures are disposed on the substrate in the first region. The protective structure conformally covers a sidewall of one of the first gate structures adjacent to the second region. The protective structure includes a lower portion and an upper portion disposed on the lower portion. The lower portion and the upper portion have different dielectric materials. A method of forming a semiconductor device is also provided.

公开(公告)号：US11251273B2

公开(公告)日：2022-02-15

申请号：US16521311

申请日：2019-07-24

Applicant: Winbond Electronics Corp.

Inventor： Jian-Ting Chen ,  Yao-Ting Tsai ,  Jung-Ho Chang ,  Hsiu-Han Liao

IPC: H01L21/28 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3215 ,  H01L21/311 ,  H01L29/788 ,  H01L29/49

Abstract: A non-volatile memory device and its manufacturing method are provided. The method includes the following steps. A plurality of isolation structures are formed in a substrate. A first polycrystalline silicon layer is formed in the substrate and between two adjacent isolation structures. A first implantation process is performed to implant a first dopant into the first polycrystalline silicon layer and the isolation structures. A portion of each of the isolation structures is partially removed, and the remaining portion of each of the isolation structures has a substantially flat top surface. An annealing process is performed after partially removing the isolation structures to uniformly diffuse the first dopant in the first polycrystalline silicon layer. A dielectric layer is formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer is formed on the dielectric layer.

公开(公告)号：US12040412B2

公开(公告)日：2024-07-16

申请号：US17375000

申请日：2021-07-14

Applicant: Winbond Electronics Corp.

Inventor： Yu-Lung Wang ,  Yao-Ting Tsai ,  Jian-Ting Chen ,  Yuan-Huang Wei

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

CPC classification number: H01L29/788 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/6653 ,  H10B41/30

Abstract: Provided is a semiconductor device including a substrate, multiple first gate structures, and a protective structure. The substrate includes a first region and a second region. The first gate structures are disposed on the substrate in the first region. The protective structure conformally covers a sidewall of one of the first gate structures adjacent to the second region. The protective structure includes a lower portion and an upper portion disposed on the lower portion. The lower portion and the upper portion have different dielectric materials. A method of forming a semiconductor device is also provided.

公开(公告)号：US11362098B2

公开(公告)日：2022-06-14

申请号：US17061442

申请日：2020-10-01

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Jian-Ting Chen ,  Yu-Kai Liao ,  Hsiu-Han Liao

IPC: H01L27/11517 ,  H01L29/66

Abstract: A method for manufacturing a memory device is provided. The method includes the following steps: providing a substrate; forming a plurality of first gate structures; forming a lining layer on the substrate; forming a spacer layer on the lining layer; forming a stop layer on the spacer layer; forming a first sacrificial layer on the stop layer; removing a portion of the first sacrificial layer to expose the stop layer on the first gate structures, and to expose the stop layer at the bottoms of the trenches; removing the stop layer at the bottoms of the trenches to expose the spacer layer; removing the remaining first sacrificial layer; forming a second sacrificial layer on the substrate; and removing the second sacrificial layer, and removing the spacer layer and the lining layer at the bottoms of the plurality of trenches to expose the substrate.