Invention Application
- Patent Title: USE OF A SINGLE INSTRUCTION SET ARCHITECTURE (ISA) INSTRUCTION FOR VECTOR NORMALIZATION
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Application No.: US17477939Application Date: 2021-09-17
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Publication No.: US20220147316A1Publication Date: 2022-05-12
- Inventor: Abhishek Rhisheekesan , Supratim Pal , Shashank Lakshminarayana , Subramaniam Maiyuran
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F7/552
- IPC: G06F7/552 ; G06F9/30

Abstract:
Embodiments described herein are generally directed to an improved vector normalization instruction. An embodiment of a method includes responsive to receipt by a GPU of a single instruction specifying a vector normalization operation to be performed on V vectors: (i) generating V squared length values, N at a time, by a first processing unit, by, for each N sets of inputs, each representing multiple component vectors for N of the vectors, performing N parallel dot product operations on the N sets of inputs. Generating V sets of outputs representing multiple normalized component vectors of the V vectors, N at a time, by a second processing unit, by, for each N squared length values of the V squared length values, performing N parallel operations on the N squared length values, wherein each of the N parallel operations implement a combination of a reciprocal square root function and a vector scaling function.
Public/Granted literature
- US11593069B2 Use of a single instruction set architecture (ISA) instruction for vector normalization Public/Granted day:2023-02-28
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