Invention Application
- Patent Title: VERIFICATION OF HARDWARE DESIGN FOR AN INTEGRATED CIRCUIT THAT IMPLEMENTS A FUNCTION THAT IS POLYNOMIAL IN ONE OR MORE SUB-FUNCTIONS
-
Application No.: US17501666Application Date: 2021-10-14
-
Publication No.: US20220147677A1Publication Date: 2022-05-12
- Inventor: Rachel Edmonds , Sam Elliott
- Applicant: Imagination Technologies Limited
- Applicant Address: GB Kings Langley
- Assignee: Imagination Technologies Limited
- Current Assignee: Imagination Technologies Limited
- Current Assignee Address: GB Kings Langley
- Priority: GB1905297.6 20190415,GB2016314.3 20201014
- Main IPC: G06F30/3323
- IPC: G06F30/3323

Abstract:
Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial of degree k in a sub-function p over a set of values of p, k being an integer greater than or equal to one. The methods include: verifying that an instantiation of the hardware design correctly evaluates the sub-function p; formally verifying that an instantiation of the hardware design implements a function that is polynomial of degree k in p by formally verifying that, for all values of p in the set of values of p, an instantiation of the hardware design has a constant kth difference; and verifying that an instantiation of the hardware design generates an expected output in response to each of at least e different values of p in the set of values of p, wherein e is equal to k when a value of the kth difference is predetermined and e is equal to k+1 when the value of the kth difference is not predetermined.
Public/Granted literature
Information query