Invention Application
- Patent Title: BURIED POWER RAILS WITH SELF-ALIGNED VIAS TO TRENCH CONTACTS
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Application No.: US16950240Application Date: 2020-11-17
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Publication No.: US20220157722A1Publication Date: 2022-05-19
- Inventor: Guillaume Bouche , Andy Chih-Hung Wei , Changyok Park
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L29/78 ; H01L29/66 ; H01L23/522 ; H01L27/092 ; H01L21/8238 ; H01L21/768 ; H01L29/06

Abstract:
Transistor arrangements fabricated by forming a metal gate cut as an opening that is non-selective to the gate sidewalls are disclosed. The etch process may be used to provide a power rail if the opening is at least partially filled with an electrically conductive material. Once an electrically conductive material has been deposited within the opening to form a power rail, recessing such a material in portions of the power rail that face gate stacks of various transistors may provide further improvements in terms of reduced parasitic capacitance. A mask for a trench contact to be used to electrically couple the power rail to a S/D region of a transistor may be used as a mask when the electrically conductive material of the power rail is recessed to realize a via that is self-aligned to the trench contact.
Public/Granted literature
- US12094822B2 Buried power rails with self-aligned vias to trench contacts Public/Granted day:2024-09-17
Information query
IPC分类: