Invention Application
- Patent Title: WAFER LEVEL PACKAGE
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Application No.: US17592947Application Date: 2022-02-04
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Publication No.: US20220157772A1Publication Date: 2022-05-19
- Inventor: Jinwoo PARK , Jungho PARK , Dahye KIM , Minjun BAE
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Priority: KR10-2019-0124772 20191008
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L23/31

Abstract:
Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.
Public/Granted literature
- US11894338B2 Wafer level package Public/Granted day:2024-02-06
Information query
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