公开(公告)号：US20220359507A1

公开(公告)日：2022-11-10

申请号：US17871077

申请日：2022-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongchan SUH ,  Dahye KIM

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78

Abstract: Provided is an integrated circuit device including: a plurality of fin-type active regions protruding from a top surface of a substrate and extending in a first horizontal direction; at least one semiconductor layer, each including a lower semiconductor layer and an upper semiconductor layer sequentially stacked on at least one of the plurality of fin-type active regions; and a plurality of gate electrodes extending in a second horizontal direction crossing the first horizontal direction on the plurality of fin-type active regions, wherein the lower semiconductor layer includes a same material as a material of the upper semiconductor layer, and wherein a semiconductor interface is provided between the lower semiconductor layer and the upper semiconductor layer.

公开(公告)号：US20230100189A1

公开(公告)日：2023-03-30

申请号：US17730928

申请日：2022-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dahye KIM ,  Sujin JUNG ,  Ingyu JANG ,  Jinbum KIM

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417

Abstract: A semiconductor device includes a fin-type active region that protrudes from a substrate and extends in a first direction, a plurality of channel layers on the fin-type active region that are spaced apart from each other in a second direction that is perpendicular to an upper surface of the substrate, a gate structure that intersects the fin-type active region, extends in the second direction, and surrounds each of the plurality of channel layers in a third direction, fence spacers on side surfaces of the fin-type active region in the second direction on sides of the gate structure and extending in the second direction, and a source/drain region between the fence spacers on the fin-type active region at sides of the gate structure, connected to each of the plurality of channel layers, and having voids in side surfaces adjacent the fence spacers.

公开(公告)号：US20210104489A1

公开(公告)日：2021-04-08

申请号：US16869988

申请日：2020-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo PARK ,  Jungho PARK ,  Dahye KIM ,  Minjun BAE

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.

公开(公告)号：US20240413246A1

公开(公告)日：2024-12-12

申请号：US18809745

申请日：2024-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun KIM ,  Dahye KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Dongwoo KIM ,  Seunghun LEE

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US20220157772A1

公开(公告)日：2022-05-19

申请号：US17592947

申请日：2022-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo PARK ,  Jungho PARK ,  Dahye KIM ,  Minjun BAE

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

Abstract: Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.

公开(公告)号：US20220005946A1

公开(公告)日：2022-01-06

申请号：US17192301

申请日：2021-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun KIM ,  Dahye KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Dongwoo KIM ,  Seunghun LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US20200381427A1

公开(公告)日：2020-12-03

申请号：US16704448

申请日：2019-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongchan SUH ,  Dahye KIM

IPC: H01L27/088 ,  H01L21/8234

Abstract: Provided is an integrated circuit device including: a plurality of fin-type active regions protruding from a top surface of a substrate and extending in a first horizontal direction; at least one semiconductor layer, each including a lower semiconductor layer and an upper semiconductor layer sequentially stacked on at least one of the plurality of fin-type active regions; and a plurality of gate electrodes extending in a second horizontal direction crossing the first horizontal direction on the plurality of fin-type active regions, wherein the lower semiconductor layer includes a same material as a material of the upper semiconductor layer, and wherein a semiconductor interface is provided between the lower semiconductor layer and the upper semiconductor layer.

公开(公告)号：US20240038842A1

公开(公告)日：2024-02-01

申请号：US18119037

申请日：2023-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungbin CHUN ,  Gyeom KIM ,  Dahye KIM ,  Youngkwang KIM ,  Jinbum KIM

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66439

Abstract: An integrated circuit (IC) device includes a fin-type active region on a substrate, a pair of nanosheets on the fin-type active region, a gate line surrounding the pair of nanosheets, the gate line including a sub-gate portion between the pair of nanosheets, a source/drain region contacting the pair of nanosheets, and a gate dielectric film between the gate line and the pair of nanosheets and between the gate line and the source/drain region, wherein the source/drain region includes a first blocking layer between the pair of nanosheets, the first blocking layer including an edge barrier enhancing portion facing the sub-gate portion, and a second blocking layer, wherein the first blocking layer includes a portion that intermittently extends in the vertical direction.

公开(公告)号：US20240006503A1

公开(公告)日：2024-01-04

申请号：US18128417

申请日：2023-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeom KIM ,  Jinbum KIM ,  Dahye KIM ,  Kyungbin CHUN

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/0673

Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate including an active region; a gate structure intersecting the active region on the substrate; channel layers on the active region, spaced apart from each other and surrounded by the gate structure; and a source/drain region on the active region adjacent the gate structure and connected to the plurality of channel layers. The source/drain region includes: a first semiconductor layer on side surfaces of the channel layers; a diffusion barrier layer on an upper region of the first semiconductor layer and including carbon, wherein an upper surface of a first channel layer that is a lowermost channel layer among the plurality of channel layers is provided between the substrate and a lower end of the diffusion barrier layer; and a second semiconductor layer on the diffusion barrier layer and the first semiconductor layer.

公开(公告)号：US20230268441A1

公开(公告)日：2023-08-24

申请号：US18307279

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun KIM ,  Dahye KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Dongwoo KIM ,  Seunghun LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/41791 ,  H01L29/6681 ,  H01L21/823431 ,  H01L29/045

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.