- 专利标题: MANAGEMENT OF A LOW-POWER MODE
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申请号: US17517382申请日: 2021-11-02
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公开(公告)号: US20220164016A1公开(公告)日: 2022-05-26
- 发明人: Gerald Baeza , Pascal Paillet , Loic Pallardy
- 申请人: STMicroelectronics (Grand Ouest) SAS
- 申请人地址: FR Le Mans
- 专利权人: STMicroelectronics (Grand Ouest) SAS
- 当前专利权人: STMicroelectronics (Grand Ouest) SAS
- 当前专利权人地址: FR Le Mans
- 优先权: FR2011958 20201120
- 主分类号: G06F1/324
- IPC分类号: G06F1/324 ; G06F1/3206
摘要:
In an embodiment a method for managing a low-power mode of an electronic device includes at a first request for transitioning an electronic device to a low-power mode, storing values of a first counter and a second counter of the electronic device on a first edge of a first clock and at a second request for transitioning the electronic device out of the low-power mode calculating a number of periods of a second clock between a second edge of the first clock and the first edge, the second edge being later than the first edge and updating the value of the second counter with a calculated value, wherein the first clock drives the first counter and the second clock drives the second counter, the second clock being faster than the first clock.
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