-
公开(公告)号：US20240214010A1
公开(公告)日：2024-06-27
申请号：US18392372
申请日：2023-12-21
发明人： Francois Sittler , Patrick Guyard
CPC分类号： H04B1/0096 , H04B1/0014 , H04B1/1607
摘要： The present disclosure relates to a method for demodulating a RF signal comprising the steps of: detecting if an analog to digital converter (ADC) of a Near Zero Intermediate Frequency (NZIF) receiver is in a clipping state; and if yes: determining and storing a first value (RSSI1) representative of the energy of a received signal demodulated by the Near Zero Intermediate Frequency (NZIF) receiver using a first intermediate frequency (IF1); determining and storing a second value (RSSI2) representative of the energy of the received signal demodulated by the Near Zero Intermediate Frequency (NZIF) receiver using a second intermediate frequency (IF2) corresponding to the opposite value of the first intermediate frequency (IF1), selecting the intermediate frequency corresponding to the lowest value of said first and second values.
-
2.发明授权公开(公告)号：US11928339B2
公开(公告)日：2024-03-12
申请号：US17825975
申请日：2022-05-26
发明人： Frederic Ruelle , Michel Jaouen
IPC分类号： G06F3/06
CPC分类号： G06F3/062 , G06F3/0604 , G06F3/064 , G06F3/0679
摘要： System, method, and circuitry for generating content for a programmable computing device based on user-selected memory regions. Contiguous regions that share memory access attributes are merged, interleaved contiguous regions that share at least one nested attribute are defined into combined regions, and remaining regions are defined as separate independent regions. A memory protection unit (MPU) region size closest to a size of each defined region is identified. If the start address of each region aligns with the address structure of the MPU region size, then those regions are assigned to MPU regions having the MPU region size; otherwise, another MPU size that aligns with the size of the regions is selected and those regions are assigned to MPU regions having that size. Content is generated to configure settings of MPU regions of the programmable computing device for the merged contiguous regions, the combined region, and the independent regions.
-
公开(公告)号：US11876732B2
公开(公告)日：2024-01-16
申请号：US17100505
申请日：2020-11-20
申请人： STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
发明人： Daniel Olson , Loic Pallardy , Nicolas Anquet
IPC分类号： H04L41/0803 , H04L49/109 , G06F21/85
CPC分类号： H04L49/109 , G06F21/85 , H04L41/0803
摘要： System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.
-
公开(公告)号：US20240004804A1
公开(公告)日：2024-01-04
申请号：US18346512
申请日：2023-07-03
发明人： Loic Pallardy , Lionel Debieve
CPC分类号： G06F12/1458 , G06F21/64
摘要： The method for managing access rights of memory regions of a memory comprises assigning an execution permission status for each memory region in a firewall device dedicated to the memory, so that the content of a memory region having an executable status is capable of being executed by a processor, and the content of a memory region having a non-executable status cannot be executed by the processor.
-
公开(公告)号：US11775037B2
公开(公告)日：2023-10-03
申请号：US17540041
申请日：2021-12-01
发明人： Loic Pallardy , Michael Soulie
IPC分类号： G06F1/24 , G06F9/4401 , G06F13/40 , G06F11/14 , G06F15/78
CPC分类号： G06F1/24 , G06F9/4401 , G06F11/1441 , G06F13/4068 , G06F15/7807 , G06F2213/40
摘要： The method for resetting a master device, configured to initiate transactions on a bus of a system on a chip, includes monitoring a completed or not state of the transactions initiated by the master device. In the case of reception of a command to reset the master device, the method includes a transmission of an effective reset command to the master device when the transactions initiated by the master device are in the completed state.
-
公开(公告)号：US11700174B2
公开(公告)日：2023-07-11
申请号：US16951198
申请日：2020-11-18
发明人： Nicolas Anquet , Loic Pallardy
IPC分类号： H04L41/0803 , H04L41/0813 , H04L49/109 , G06F15/173 , G06F15/177 , G06F21/85
CPC分类号： H04L41/0813 , G06F15/177 , G06F15/17306 , H04L41/0803 , H04L49/109 , G06F21/85
摘要： System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.
-
公开(公告)号：US11630665B2
公开(公告)日：2023-04-18
申请号：US17404835
申请日：2021-08-17
发明人： Lionel Cimaz
摘要： A method executes instructions, each corresponding to switching a signal, a delay, and a condition selected among first, second, or third conditions. Each execution includes performing, after the delay, switching the signal if the condition is the first condition, if the condition is the second condition and a flag is in an active state, or if the condition is the third condition and the flag is in an inactive state, or not switching the signal if the condition is the second condition and the flag is in the inactive state, or if the condition is the third condition and the flag is in the active state. A first instruction represents a first switching of a first signal, a first delay, and the second condition, and is immediately followed by a second instruction representing the first switching of the first signal, a second delay, and the third condition.
-
公开(公告)号：US11588353B2
公开(公告)日：2023-02-21
申请号：US17461305
申请日：2021-08-30
摘要： The present disclosure relates to a device comprising an inductive element and a first capacitive element series connected between a first node and a second node, a first MOS transistor connected between the first node and a third node configured to receive a reference potential, the second node being coupled directly or via a second MOS transistor to the third node, a second capacitive element connected between a fourth node and an interconnection node between the first capacitive element and the inductive element, a current generator configured to provide an AC current to the fourth node, and a switch connected between the fourth node and the third node.
-
公开(公告)号：US20220318392A1
公开(公告)日：2022-10-06
申请号：US17657027
申请日：2022-03-29
发明人： Franck Albesa , Nicolas Anquet
IPC分类号： G06F21/57 , G06F21/60 , G06F9/4401
摘要： The present disclosure relates to a method for booting a processing device, the method including: generating, by a monotonic counter and during a first boot phase, a first count value; transmitting, by the monotonic counter, the first count value to an access control circuit of a memory; reading, on the basis of the first count value, first data stored in the memory; and generating, by the monotonic counter and during a second boot phase, a second count value greater than the first count value. The access control circuit of the memory is configured so that the reading of the first data is not authorized on the basis of the second count value.
-
公开(公告)号：US20220209947A1
公开(公告)日：2022-06-30
申请号：US17553481
申请日：2021-12-16
发明人： Julien COUVRAND , William ORLANDO
IPC分类号： H04L9/08
摘要： The present description concerns an electronic system including one or a plurality of first microprocessors, a second microprocessor for securely managing first encryption keys of the first microprocessors, the second microprocessor being configured to communicate with each first microprocessor and including a first non-volatile memory having at least one second key stored therein, and for each first microprocessor, a second non-volatile memory external to the second microprocessor and containing the first keys of the first microprocessor encrypted with the second key.
-
-
-
-
-
-
-
-
-
搜索结果
134 条记录 (耗时 0.019 秒)
