An optical network on chip comprises a first optical communication link and a second communication optical link. The first communication optical link comprises a plurality of first wavelength division multiplexers (WDMs) coupled to a first processor, a plurality of second WDMs coupled to a second processor, and a plurality of first optical interconnects coupled between the plurality of first WDMs and the plurality of second WDMs. The second optical communication link comprises a plurality of first serializer-deserializers (SerDes) coupled to the first processor at one end and coupled to a plurality third WDMs at the other end, a plurality of second SerDes coupled to a memory component at one end and coupled to a plurality of fourth WDMs at the other end, and a plurality of second optical interconnects coupled between the plurality of third WDMs and the plurality of fourth WDMs.