Invention Application
- Patent Title: DEBUGGING ARCHITECTURE FOR SYSTEM IN PACKAGE COMPOSED OF MULTIPLE SEMICONDUCTOR CHIPS
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Application No.: US17132891Application Date: 2020-12-23
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Publication No.: US20220198110A1Publication Date: 2022-06-23
- Inventor: Shanker Raman NAGESH , Ashok JAGANNATHAN
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F30/33
- IPC: G06F30/33

Abstract:
A method is described. The method includes maintaining a synchronized count value in each of a plurality of logic chips within a same package. The method includes comparing the count value against a same looked for count value in each of the plurality of logic chips. The method includes each of the plurality of logic chips recording in its respective local memory at least some of its state information in response to each of the plurality of logic chips recognizing within a same cycle that the count value has reached the same looked for count value.
Public/Granted literature
- US12204834B2 Debugging architecture for system in package composed of multiple semiconductor chips Public/Granted day:2025-01-21
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