DEBUGGING ARCHITECTURE FOR SYSTEM IN PACKAGE COMPOSED OF MULTIPLE SEMICONDUCTOR CHIPS
Abstract:
A method is described. The method includes maintaining a synchronized count value in each of a plurality of logic chips within a same package. The method includes comparing the count value against a same looked for count value in each of the plurality of logic chips. The method includes each of the plurality of logic chips recording in its respective local memory at least some of its state information in response to each of the plurality of logic chips recognizing within a same cycle that the count value has reached the same looked for count value.
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