Invention Application
- Patent Title: SECURE MEMORY
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Application No.: US17556039Application Date: 2021-12-20
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Publication No.: US20220199133A1Publication Date: 2022-06-23
- Inventor: Faress TISSAFI DRISSI
- Applicant: STMicroelectronics SA
- Applicant Address: FR Montrouge
- Assignee: STMicroelectronics SA
- Current Assignee: STMicroelectronics SA
- Current Assignee Address: FR Montrouge
- Priority: FR2014086 20201223
- Main IPC: G11C7/24
- IPC: G11C7/24 ; G11C11/419

Abstract:
A memory includes memory cells arranged in rows and in columns, with at least one bit line for each column being coupled to the memory cells of the column. A read/write circuit is coupled to the bit lines and is configured to receive, for each column, a binary datum to be stored in one of the memory cells of the column. The read/write circuit includes, for each column, a latch configured to store a bit of a key, and an encryption circuit configured to encrypt the received binary datum with the bit of the key to provide encrypted binary datum. The read/write circuit controls the bit line to thereby store the encrypted binary datum.
Public/Granted literature
- US11978530B2 Secure memory Public/Granted day:2024-05-07
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