公开(公告)号：US20220199133A1

公开(公告)日：2022-06-23

申请号：US17556039

申请日：2021-12-20

Applicant: STMicroelectronics SA

Inventor： Faress TISSAFI DRISSI

IPC: G11C7/24 ,  G11C11/419

Abstract: A memory includes memory cells arranged in rows and in columns, with at least one bit line for each column being coupled to the memory cells of the column. A read/write circuit is coupled to the bit lines and is configured to receive, for each column, a binary datum to be stored in one of the memory cells of the column. The read/write circuit includes, for each column, a latch configured to store a bit of a key, and an encryption circuit configured to encrypt the received binary datum with the bit of the key to provide encrypted binary datum. The read/write circuit controls the bit line to thereby store the encrypted binary datum.

公开(公告)号：US20210074352A1

公开(公告)日：2021-03-11

申请号：US17011634

申请日：2020-09-03

Applicant: STMicroelectronics SA

Inventor： Faress TISSAFI DRISSI

IPC: G11C11/419

Abstract: Methods and devices for adjusting a read threshold voltage of bitlines are provided. One such method includes adjusting a read threshold voltage of bitlines coupled to memory points of a memory circuit. The read threshold voltage is initially set to a first value. First data are written in the memory points and second data are read from the memory points. The second data are compared to the first data, and the threshold voltage is decreased by a second value in response to a comparison error of one of the second data with the corresponding first data.