Disclosed are a gate driver circuit having a reduced size, and a display device including the same. The gate driver circuit includes a plurality of stage circuits. Each stage circuit supplies a gate signal to each of gate lines arranged in a display panel, and includes a M node, a Q node, a QH node, and a QB node. Each stage circuit includes a gate signal output module configured to operate based on a voltage level of the Q node or a voltage level of the QB node to output first to j-th gate signals based on first to j-th scan clock signals or a first low-potential voltage.