Invention Application
- Patent Title: CONDUCTIVE PLATE STRESS REDUCTION FEATURE
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Application No.: US17138981Application Date: 2020-12-31
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Publication No.: US20220208692A1Publication Date: 2022-06-30
- Inventor: Tianyi Luo , Jonathan Almeria Noquil , Satyendra Singh Chauhan , Osvaldo Jorge Lopez , Lance Cole Wright
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L23/495 ; H01L21/48 ; H01L21/56

Abstract:
A packaged electronic device includes a semiconductor die, a conductive plate coupled to a lead, a solder structure and a package structure. The semiconductor die has opposite first and second sides and a terminal exposed along the second side. The conductive plate has opposite first and second sides and an indent that extends into the first side, the conductive plate, and the solder structure extends between the second side of the semiconductor die and the first side of the conductive plate to electrically couple the conductive plate to the terminal, and the solder structure extends into the indent. The package structure encloses the semiconductor die, the conductive plate and a portion of the lead.
Public/Granted literature
- US11658130B2 Conductive plate stress reduction feature Public/Granted day:2023-05-23
Information query
IPC分类: