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公开(公告)号：US11177246B2
公开(公告)日：2021-11-16
申请号：US16546475
申请日：2019-08-21
发明人： Osvaldo Jorge Lopez , Walter Hans Paul Schroen , Jonathan Almeria Noquil , Thomas Eugene Grebs , Simon John Molloy
IPC分类号： H01L25/16 , H01L31/028 , H01L31/042 , H01L31/0216 , H01L27/082 , H01L27/088 , H01L31/18 , H01L31/02 , H01L25/00 , H01L29/06 , H01L23/053 , H01L23/06 , H01L23/13 , H01L23/14 , H01L21/50 , H01L23/00 , H01L25/18 , H01L25/04 , H01L23/498
摘要： A self-powered electronic system comprises a first chip of single-crystalline semiconductor embedded in a second chip of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container bordered by ridges. The flat side of the slab includes a heavily n-doped region forming a pn-junction with the p-type bulk. A metal-filled deep silicon via through the p-type ridge connects the n-region with the terminal on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.
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公开(公告)号：US20210265246A1
公开(公告)日：2021-08-26
申请号：US17318974
申请日：2021-05-12
摘要： A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.
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公开(公告)号：US09859261B2
公开(公告)日：2018-01-02
申请号：US15465455
申请日：2017-03-21
发明人： Osvaldo Jorge Lopez , Walter Hans Paul Schroen , Jonathan Almeria Noquil , Thomas Eugene Grebs , Simon John Molloy
IPC分类号： H01L25/16 , H01L31/02 , H01L31/0216 , H01L31/028 , H01L31/042 , H01L31/18 , H01L27/082 , H01L27/088 , H01L25/00
CPC分类号： H01L25/167 , H01L21/50 , H01L23/053 , H01L23/06 , H01L23/13 , H01L23/147 , H01L23/49844 , H01L24/83 , H01L25/18 , H01L25/50 , H01L27/082 , H01L27/088 , H01L29/0657 , H01L31/02008 , H01L31/02168 , H01L31/028 , H01L31/042 , H01L31/1804 , H01L31/1868 , H01L2224/83851 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01079 , H01L2924/04642 , H01L2924/04941 , H01L2924/05042 , H01L2924/05442 , H01L2924/10155 , H01L2924/1305 , H01L2924/13091 , H01L2924/1425 , H01L2924/1427 , H01L2924/15
摘要： A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.
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公开(公告)号：US09818662B2
公开(公告)日：2017-11-14
申请号：US14702031
申请日：2015-05-01
IPC分类号： H01L23/14 , H01L23/13 , H01L21/50 , H01L21/98 , H01L21/52 , H01L25/16 , H01L21/48 , H01L25/00 , H01L21/78
CPC分类号： H01L23/147 , H01L21/481 , H01L21/78 , H01L23/057 , H01L23/08 , H01L23/13 , H01L25/16 , H01L25/165 , H01L25/50 , H01L2924/0002 , H01L2924/00
摘要： A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.
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5.发明申请SILICON PACKAGE FOR EMBEDDED ELECTRONIC SYSTEM HAVING STACKED SEMICONDUCTOR CHIPS 审中-公开具有堆叠半导体芯片的嵌入式电子系统的硅胶包装公开(公告)号：US20160172338A1
公开(公告)日：2016-06-16
申请号：US15053089
申请日：2016-02-25
IPC分类号： H01L25/065
CPC分类号： H01L25/0657 , H01L21/50 , H01L23/053 , H01L23/06 , H01L23/13 , H01L23/147 , H01L23/49844 , H01L24/83 , H01L24/97 , H01L25/0652 , H01L25/071 , H01L25/074 , H01L25/18 , H01L25/50 , H01L29/0657 , H01L2224/06181 , H01L2224/2919 , H01L2224/32145 , H01L2224/83851 , H01L2224/94 , H01L2224/97 , H01L2225/00 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06589 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01079 , H01L2924/04642 , H01L2924/04941 , H01L2924/05042 , H01L2924/05442 , H01L2924/10155 , H01L2924/10253 , H01L2924/10271 , H01L2924/1032 , H01L2924/10329 , H01L2924/1033 , H01L2924/1037 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/1425 , H01L2924/1427 , H01L2924/15156 , H01L2924/157 , H01L2224/83
摘要： An electronic system comprises a first chip of single-crystalline semiconductor shaped as a hexahedron and including a first electronic device embedded in a second chip of single-crystalline semiconductor shaped as a container having a slab bordered by retaining walls, and including a second electronic device. The container shaped as a slab bordered by the retaining walls and including conductive traces and terminals. The first chip is attached to the slab of second chip, forming nested chips. The first and second chips embedded in the container. The nested first and second chips are operable as an electronic system and the container is operable as the package of the system.
摘要翻译： 电子系统包括形成为六面体的单晶半导体的第一芯片，并且包括第一电子器件，所述第一电子器件嵌入在形成为容器的单晶半导体的第二芯片中，所述第一芯片具有由保持壁邻接的板，并且包括第二电子器件 。 容器形成为由挡土墙毗邻并包括导电迹线和端子的平板。 第一芯片连接到第二芯片的板上，形成嵌套芯片。 第一个和第二个芯片嵌入容器。 嵌套的第一和第二芯片可操作为电子系统，并且容器可操作为系统的封装。
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6.发明授权DC-DC converter having terminals of semiconductor chips directly attachable to circuit board 有权DC-DC转换器具有可直接连接到电路板的半导体芯片的端子公开(公告)号：US09305872B2
公开(公告)日：2016-04-05
申请号：US14800903
申请日：2015-07-16
CPC分类号： H01L23/49575 , H01L21/563 , H01L23/3107 , H01L23/49503 , H01L23/4952 , H01L23/49524 , H01L23/49548 , H01L23/49551 , H01L23/49562 , H01L23/49568 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L24/85 , H01L25/072 , H01L25/16 , H01L25/50 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/3716 , H01L2224/37599 , H01L2224/40245 , H01L2224/45015 , H01L2224/48106 , H01L2224/48108 , H01L2224/48137 , H01L2224/48247 , H01L2224/49173 , H01L2224/73221 , H01L2224/83801 , H01L2224/8385 , H01L2224/85 , H01L2924/00014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1425 , H01L2924/1426 , H01L2924/15724 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H02M3/155 , H01L2924/00 , H01L2224/45099 , H01L2924/20752 , H01L2924/00012 , H01L2924/01028 , H01L2224/05599
摘要： A power supply system has a QFN leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline suitable for attaching side-by-side the sync and the control FET semiconductor chips. The input terminal of the control FET and the grounded output terminal of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip is vertically stacked to the opposite pad surface and encapsulated in a packaging compound.
摘要翻译： 电源系统具有带引线和焊盘的QFN引线框架。 面对电路板的焊盘表面具有凹陷的部分，其深度和轮廓适合于并置并联和控制FET半导体芯片。 控制FET的输入端子和同步FET的接地输出端子与焊盘（开关节点端子）的未凹入部分共面，使得所有端子可以直接附接到电路板的触点。 驱动器和控制芯片垂直地堆叠到相对的焊盘表面并且封装在封装复合体中。
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7.发明申请Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips 有权集成了具有垂直堆叠半导体芯片的多输出功率转换器公开(公告)号：US20160064313A1
公开(公告)日：2016-03-03
申请号：US14938422
申请日：2015-11-11
发明人： Marie Denison , Brian Ashley Carpenter , Osvaldo Jorge Lopez , Juan Alejandro Herbsommer , Jonathan Noquil
IPC分类号： H01L23/495 , H01L23/00
CPC分类号： H01L23/49575 , H01L21/50 , H01L21/561 , H01L23/49524 , H01L23/49562 , H01L23/49838 , H01L24/29 , H01L24/32 , H01L24/34 , H01L24/36 , H01L24/37 , H01L24/38 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/84 , H01L24/97 , H01L25/0657 , H01L25/072 , H01L25/16 , H01L25/18 , H01L25/50 , H01L2224/29101 , H01L2224/32245 , H01L2224/37147 , H01L2224/40095 , H01L2224/40137 , H01L2224/40139 , H01L2224/40145 , H01L2224/40245 , H01L2224/45014 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/83191 , H01L2224/84801 , H01L2224/8484 , H01L2224/8485 , H01L2924/00014 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/1301 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/15724 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/01028 , H01L2924/014 , H01L2924/20752
摘要： A electronic multi-output device having a substrate including a pad and pins. A composite first chip has a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface. Patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. The second terminals are connected by discrete first and second metal clips to respective substrate pins. A composite second chip has a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to be vertically attached with its first terminals to the first and second clips, respectively. The third terminals are connected by discrete clips to respective substrate pins. The common second terminal is connected by a common clip to a substrate pin.
摘要翻译： 一种电子多输出装置，具有包括垫和销的基板。 复合第一芯片具有集成的第一和第二晶体管，使得晶体管的第一端子在一个芯片表面上合并成公共端子。 图案化的第二和第三端子位于相对的芯片表面上。 公共第一端子附接到衬底垫。 第二端子通过分立的第一和第二金属夹连接到相应的衬底引脚。 复合第二芯片具有集成的第三和第四晶体管，使得晶体管的第二端子在一个芯片表面上合并成公共端子。 图案化的第一和第三端子在相对的芯片表面上。 第二芯片被翻转以分别与其第一端子垂直地附接到第一和第二夹子。 第三端子通过离散夹子连接到相应的衬底引脚。 公共第二端子通过公共夹子连接到衬底引脚。
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8.发明申请Stacked Synchronous Buck Converter Having Chip Embedded in Outside Recess of Leadframe 审中-公开堆叠式同步降压转换器，将芯片嵌入到引线框架的外部凹槽中公开(公告)号：US20160027722A1
公开(公告)日：2016-01-28
申请号：US14878408
申请日：2015-10-08
IPC分类号： H01L23/495 , H01L21/56 , H01L23/31 , H01L23/00 , H01L25/00 , H01L25/065
CPC分类号： H01L23/49575 , H01L21/56 , H01L23/3107 , H01L23/49503 , H01L23/49524 , H01L23/49541 , H01L23/49548 , H01L23/49562 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/84 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L25/165 , H01L25/50 , H01L2224/27312 , H01L2224/291 , H01L2224/2919 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/32145 , H01L2224/32147 , H01L2224/32148 , H01L2224/32245 , H01L2224/33181 , H01L2224/37013 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40499 , H01L2224/4103 , H01L2224/41051 , H01L2224/48091 , H01L2224/48106 , H01L2224/48111 , H01L2224/48145 , H01L2224/48247 , H01L2224/4911 , H01L2224/49111 , H01L2224/49171 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/73271 , H01L2224/83191 , H01L2224/83192 , H01L2224/83439 , H01L2224/83444 , H01L2224/83455 , H01L2224/83464 , H01L2224/83801 , H01L2224/83815 , H01L2224/8385 , H01L2224/83851 , H01L2224/83862 , H01L2224/8391 , H01L2224/84439 , H01L2224/84444 , H01L2224/84447 , H01L2224/84455 , H01L2224/84464 , H01L2224/84801 , H01L2224/84815 , H01L2224/8491 , H01L2224/85439 , H01L2224/85444 , H01L2224/85455 , H01L2224/85464 , H01L2224/92147 , H01L2224/92157 , H01L2224/9221 , H01L2224/92242 , H01L2224/92247 , H01L2224/92252 , H01L2225/0651 , H01L2924/00014 , H01L2924/1306 , H01L2924/13091 , H01L2924/1425 , H01L2924/14252 , H01L2924/1426 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/20752 , H01L2224/45099 , H01L2924/00012 , H01L2924/014 , H01L2924/0665 , H01L2924/07811 , H01L2924/07812 , H01L2224/83447 , H01L2224/83 , H01L2224/84 , H01L2224/85 , H01L2224/27
摘要： A system has a leadframe with leads and a pad. The pad surface having a portion recessed with a depth and an outline suitable for attaching a semiconductor chip. A first chip is vertically stacked to the opposite pad surface. A clip is vertically stacked on the first chip and tied to a lead. A second chip has a terminal attached to the recessed portion and terminals co-planar with the un-recessed portion. A second chip is attached to the clip.
摘要翻译： 系统具有带引线和焊盘的引线框架。 焊盘表面具有凹陷的部分，其具有适于附接半导体芯片的深度和轮廓。 第一芯片垂直堆叠到相对的焊盘表面。 一个夹子垂直堆放在第一个芯片上并绑在一个引线上。 第二芯片具有附接到凹部的端子和与未凹部共同的端子。 第二个芯片连接到夹子上。
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9.发明授权DC-DC converter having terminals of semiconductor chips directly attachable to circuit board 有权DC-DC转换器具有可直接连接到电路板的半导体芯片的端子公开(公告)号：US09171828B2
公开(公告)日：2015-10-27
申请号：US14481204
申请日：2014-09-09
IPC分类号： H01L21/50 , H01L25/16 , H01L25/00 , H01L23/495 , H01L23/00 , H01L21/56 , H01L25/07 , H01L23/31
CPC分类号： H01L23/49575 , H01L21/563 , H01L23/3107 , H01L23/49503 , H01L23/4952 , H01L23/49524 , H01L23/49548 , H01L23/49551 , H01L23/49562 , H01L23/49568 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L24/85 , H01L25/072 , H01L25/16 , H01L25/50 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/3716 , H01L2224/37599 , H01L2224/40245 , H01L2224/45015 , H01L2224/48106 , H01L2224/48108 , H01L2224/48137 , H01L2224/48247 , H01L2224/49173 , H01L2224/73221 , H01L2224/83801 , H01L2224/8385 , H01L2224/85 , H01L2924/00014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1425 , H01L2924/1426 , H01L2924/15724 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H02M3/155 , H01L2924/00 , H01L2224/45099 , H01L2924/20752 , H01L2924/00012 , H01L2924/01028 , H01L2224/05599
摘要： A power supply system (200) has a QFN leadframe with leads and a pad (201). The pad surface facing a circuit board has a portion recessed with a depth (270) and an outline suitable for attaching side-by-side the sync (210) and the control (220) FET semiconductor chips. The input terminal (220a) of the control FET and the grounded output terminal (210a) of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip (230) is vertically stacked to the opposite pad surface and encapsulated in a packaging compound (290).
摘要翻译： 电源系统（200）具有带引线的QFN引线框和焊盘（201）。 面对电路板的焊盘表面具有凹陷深度（270）的部分和适合于并联并联（210）和控制（220）FET半导体芯片的轮廓。 控制FET的输入端子（220a）和同步FET的接地输出端子（210a）与焊盘的未凹入部分（开关节点端子）共面，使得所有端子可以直接附接到 电路板。 驱动器和控制芯片（230）垂直地堆叠到相对的焊盘表面并且封装在封装化合物（290）中。
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10.发明申请Stacked Synchronous Buck Converter Having Chip Embedded in Outside Recess of Leadframe 有权堆叠式同步降压转换器，将芯片嵌入到引线框架的外部凹槽中公开(公告)号：US20150221584A1
公开(公告)日：2015-08-06
申请号：US14173147
申请日：2014-02-05
CPC分类号： H01L23/49575 , H01L21/56 , H01L23/3107 , H01L23/49503 , H01L23/49524 , H01L23/49541 , H01L23/49548 , H01L23/49562 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/84 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L25/165 , H01L25/50 , H01L2224/27312 , H01L2224/291 , H01L2224/2919 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/32145 , H01L2224/32147 , H01L2224/32148 , H01L2224/32245 , H01L2224/33181 , H01L2224/37013 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40499 , H01L2224/4103 , H01L2224/41051 , H01L2224/48091 , H01L2224/48106 , H01L2224/48111 , H01L2224/48145 , H01L2224/48247 , H01L2224/4911 , H01L2224/49111 , H01L2224/49171 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/73271 , H01L2224/83191 , H01L2224/83192 , H01L2224/83439 , H01L2224/83444 , H01L2224/83455 , H01L2224/83464 , H01L2224/83801 , H01L2224/83815 , H01L2224/8385 , H01L2224/83851 , H01L2224/83862 , H01L2224/8391 , H01L2224/84439 , H01L2224/84444 , H01L2224/84447 , H01L2224/84455 , H01L2224/84464 , H01L2224/84801 , H01L2224/84815 , H01L2224/8491 , H01L2224/85439 , H01L2224/85444 , H01L2224/85455 , H01L2224/85464 , H01L2224/92147 , H01L2224/92157 , H01L2224/9221 , H01L2224/92242 , H01L2224/92247 , H01L2224/92252 , H01L2225/0651 , H01L2924/00014 , H01L2924/1306 , H01L2924/13091 , H01L2924/1425 , H01L2924/14252 , H01L2924/1426 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/20752 , H01L2224/45099 , H01L2924/00012 , H01L2924/014 , H01L2924/0665 , H01L2924/07811 , H01L2924/07812 , H01L2224/83447 , H01L2224/83 , H01L2224/84 , H01L2224/85 , H01L2224/27
摘要： A power supply system (200) has a QFN leadframe with leads and a pad (201, switch node terminal); a pad surface having a portion recessed with a depth (270) and an outline suitable for attaching a semiconductor chip. A first FET chip (220) is vertically stacked to the opposite pad surface. A clip (240) is vertically stacked on the first FET chip and tied to a lead (202, grounded output terminal). A second FET chip (210) has its source terminal attached to the recessed portion and its drain (210a, input terminal) and gate (210b) terminals co-planar with the un-recessed portion. A driver-and-controller chip (230) is attached to the clip. Packaging compound (290) encapsulates the parts but leaves a pad surface and the drain and gate terminals of the second FET chip un-encapsulated.
摘要翻译： 电源系统（200）具有带导线和焊盘（201，开关节点端子）的QFN引线框架; 垫表面，其具有凹入深度（270）的部分和适合于附接半导体芯片的轮廓。 第一FET芯片（220）垂直地堆叠到相对的焊盘表面。 夹子（240）垂直堆叠在第一FET芯片上并连接到引线（202，接地输出端子）。 第二FET芯片（210）的源极端子连接到凹部，其漏极（210a，输入端子）和栅极（210b）端子与未凹入部分共面。 驱动器和控制器芯片（230）附接到夹子。 包装化合物（290）封装部件但留下焊盘表面，并且第二FET芯片的漏极和栅极端子未封装。
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