Invention Application
- Patent Title: Network-On-Chip Topology Generation
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Application No.: US17695947Application Date: 2022-03-16
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Publication No.: US20220210056A1Publication Date: 2022-06-30
- Inventor: Nitin Kumar Agarwal , Anup Gangwar , Honnahuggi Harinath Venkata Naga Ambica Prasad , Ravishankar Sreedharan , Narayana Sri Harsha Gade
- Applicant: Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Main IPC: H04L45/00
- IPC: H04L45/00 ; H04L45/42 ; H04L45/02 ; H04L45/24

Abstract:
A computer-based method and system for synthesizing a Network-on-Chip (NoC) is provided. One method includes determining physical data, device data, bridge data, traffic data and domain data based on an input specification for the NoC; assigning a domain to each bridge port; partitioning each traffic flow into one of a plurality of bins based on the bridge port domain assignments and the domain crossing constraints; creating a virtual node at each bridge port endpoint; generating a candidate topology for each bin based on the physical data, the device data, the bridge data, the traffic data, the domain data and the virtual nodes, each candidate topology including bridge ports, a tree of routers, routes and connections; and generating a final topology by merging the candidate topologies.
Public/Granted literature
- US12250145B2 Network-on-chip topology generation Public/Granted day:2025-03-11
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