Network-on-chip link size generation

    公开(公告)号:US11050672B2

    公开(公告)日:2021-06-29

    申请号:US16518259

    申请日:2019-07-22

    申请人: Arm Limited

    摘要: The present disclosure advantageously provides a system, a computer-readable medium and a method for synthesizing a Network-on-Chip (NoC). A plurality of route feature vectors are determined based on a network configuration for the NoC. The network configuration includes bridge ports, routers, connections and routes. A link size is determined for each router by providing route feature vectors to a supervised learning-based (SLB) model. The SLB model generates a plurality of route label vectors based on the route feature vectors. Each route label vector is associated with a route feature vector, and includes the link size and a route position for each router. A resizer is added between a bridge and a router with different link sizes or between adjacent routers with different link sizes. Pipeline and retiming components are added based on timing. An output specification is then generated for the NoC.

    Network-On-Chip Link Size Generation

    公开(公告)号:US20210029045A1

    公开(公告)日:2021-01-28

    申请号:US16518259

    申请日:2019-07-22

    申请人: Arm Limited

    摘要: The present disclosure advantageously provides a system, a computer-readable medium and a method for synthesizing a Network-on-Chip (NoC). A plurality of route feature vectors are determined based on a network configuration for the NoC. The network configuration includes bridge ports, routers, connections and routes. A link size is determined for each router by providing route feature vectors to a supervised learning-based (SLB) model. The SLB model generates a plurality of route label vectors based on the route feature vectors. Each route label vector is associated with a route feature vector, and includes the link size and a route position for each router. A resizer is added between a bridge and a router with different link sizes or between adjacent routers with different link sizes. Pipeline and retiming components are added based on timing. An output specification is then generated for the NoC.

    Network on-chip topology generation

    公开(公告)号:US10817627B1

    公开(公告)日:2020-10-27

    申请号:US16518254

    申请日:2019-07-22

    申请人: Arm Limited

    摘要: The present disclosure provides a computer-based method and system for synthesizing a NoC. Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow. A head of line (HoL) conflict graph (HCG) is constructed based on the traffic data and the VC assignments. A color is assigned to each HCG node to minimize HoL conflicts. A traffic graph (TG) is constructed for each color based on the physical data, the bridge data, the traffic data and the HCG, and a candidate topology is generated for each color based on the respective TG. The candidate topology for each color is merged to create a merged candidate topology, and the routers within the merged candidate topology are merged to generate a final topology for the NoC.

    Network-on-chip topology generation

    公开(公告)号:US11310169B2

    公开(公告)日:2022-04-19

    申请号:US17152034

    申请日:2021-01-19

    申请人: Arm Limited

    摘要: The present disclosure provides a computer-based method and system for synthesizing a NoC. Traffic data is determined or received, and a baseline topology is generated or received. For each router in the baseline topology, a number of edge virtual channel (EVC) combinations is determined, the transmittablility of the traffic classes are determined, and, when the traffic classes are not transmittable, the router is identified. A traffic class affinity graph (TCAG) is generated for each identified router. Traffic class combinations are generated for the identified routers based on the TCAGs and EVC combinations. The traffic classes of the identified routers are merged based on the traffic class combinations. A final EVC combination for each identified router is determined based on the merged traffic classes. A final topology is generated based, at least in part, on the merged traffic classes and the final EVC combinations for the identified routers.

    Network-On-Chip Element Placement

    公开(公告)号:US20210058289A1

    公开(公告)日:2021-02-25

    申请号:US17094145

    申请日:2020-11-10

    申请人: Arm Limited

    摘要: The present disclosure provides a computer-based method and system for synthesizing a Network-on-Chip (NoC). Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow to create a plurality of VC assignments. A topology is generated, based on the physical data, the device data, the bridge data, the traffic data and the VC assignments, which includes bridge ports, routers and connections. Final locations for relocatable NoC elements (e.g., routers, etc.) are determined based on NoC element energy values for the relocatable NoC elements, and protocol-level pipelines may be inserted into the connections based on a timing parameter.

    Network-On-Chip Topology Generation

    公开(公告)号:US20210036967A1

    公开(公告)日:2021-02-04

    申请号:US17076403

    申请日:2020-10-21

    申请人: Arm Limited

    摘要: The present disclosure provides a computer-based method and system for synthesizing a NoC. Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow. A head of line (HoL) conflict graph (HCG) is constructed based on the traffic data and the VC assignments. The HGC is modified based on bridge data and the traffic data to generate a modified HCG. A plurality of traffic graphs (TGs) are constructed based on the physical data, the bridge data, the traffic data and the modified HCG. A candidate topology is generated for each TG, which includes the bridge ports, routers and connections. The candidate topologies are merged to create a merged candidate topology, and the routers within the merged candidate topology are merged to generate a final topology for the NoC.

    Virtual Channel Assignment For Topology Constrained Network-on-Chip Design

    公开(公告)号:US20200267073A1

    公开(公告)日:2020-08-20

    申请号:US16280220

    申请日:2019-02-20

    申请人: Arm Limited

    IPC分类号: H04L12/751

    摘要: Virtual channel assignment in a network is achieved by constructing a Traffic Conflict Graph (TCG) dependent upon a network interconnect topology. The TCG has vertices corresponding to traffic entries in a network specification and edges that connect pairs of vertices. An edge weight, dependent upon interconnect topology and traffic flow characteristics, is assigned to each edge. The vertices are colored using minimum or soft coloring and the virtual channels are mapped to the traffic entries, according to the resulting colors, to provide a virtual channel assignment. The TCG may be constructed by generating a vertex in the TCG to represent each traffic entry, assigning a traffic flow characteristic of a traffic entry to a corresponding vertex and generating an edge between first and second vertices when a number of ‘qualified’ common edges, across all routes for corresponding traffic entries, is greater than zero.