Invention Application
- Patent Title: DMOS FET CHIP SCALE PACKAGE AND METHOD OF MAKING THE SAME
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Application No.: US17187682Application Date: 2021-02-26
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Publication No.: US20220278009A1Publication Date: 2022-09-01
- Inventor: Yan Xun Xue , Long-Ching Wang , Hongyong Xue , Madhur Bobde , Zhiqiang Niu , Jun Lu
- Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
- Applicant Address: CA Toronto
- Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
- Current Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
- Current Assignee Address: CA Toronto
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/00 ; H01L21/78 ; H01L21/56

Abstract:
A method comprises the steps of providing a wafer; applying a redistribution layer, grinding a back side of the wafer; depositing a metal layer; and applying a singulation process. A semiconductor package comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), a redistribution layer, and a metal layer. The MOSFET comprises a source electrode, a gate electrode, a drain electrode and a plurality of partial drain plugs. The source electrode, the gate electrode, and the drain electrode are positioned at a front side of the MOSFET.
Public/Granted literature
- US11699627B2 DMOS FET chip scale package and method of making the same Public/Granted day:2023-07-11
Information query
IPC分类: