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    SEMICONDUCTOR PACKAGE HAVING HIGH METAL BUMPS AND ULTRA-THIN SUBSTRATE AND METHOD OF MAKING THE SAME
    2.
    发明申请
    SEMICONDUCTOR PACKAGE HAVING HIGH METAL BUMPS AND ULTRA-THIN SUBSTRATE AND METHOD OF MAKING THE SAME 有权

    公开(公告)号：US20250070069A1

    公开(公告)日：2025-02-27

    申请号：US18783446

    申请日：2024-07-25

    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

    Inventor： Lin Lv ,  Zhen Yang ,  Shuhua Zhou ,  Long-Ching Wang

    IPC: H01L23/00 ,  H01L21/304 ,  H01L23/31

    Abstract: A semiconductor package comprises a semiconductor substrate, a plurality of contact pads, a plurality of metal bumps, a metal layer, and a molding encapsulation. A thickness of the semiconductor substrate is less than 35 microns. A first method comprises the steps of providing a device wafer; attaching a first carrier; applying a thinning process; forming a metal layer; applying a first tape; removing the first carrier; applying a first singulation process; removing the first tape; attaching a second carrier; forming a molding encapsulation; removing the second carrier; forming a plurality of metal bumps; applying a second tape; and applying a singulation process and removing the second tape. A second method comprises the steps of providing a device wafer; attaching a carrier; applying a thinning process; forming a metal layer; forming a molding encapsulation; removing the carrier; forming a plurality of metal bumps; and applying a singulation process.

    CHIP SCALE PACKAGE (CSP) SEMICONDUCTOR DEVICE HAVING THIN SUBSTRATE
    3.
    发明公开
    CHIP SCALE PACKAGE (CSP) SEMICONDUCTOR DEVICE HAVING THIN SUBSTRATE 审中-公开

    公开(公告)号：US20230307325A1

    公开(公告)日：2023-09-28

    申请号：US17701695

    申请日：2022-03-23

    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

    Inventor： Lin Lv ,  Shuhua Zhou ,  Long-Ching Wang ,  Jun Lu

    IPC: H01L23/482 ,  H01L23/29

    CPC classification number: H01L23/4827 ,  H01L23/295 ,  H01L27/088

    Abstract: A semiconductor device comprises a semiconductor substrate, a plurality of metal layers, an adhesive layer, a compound layer, and a plurality of contact pads. A thickness of the semiconductor substrate is in a range from 15 μm to 35 μm. A thickness of the compound layer is larger than the thickness of the semiconductor substrate. A coefficient of thermal expansion of the compound layer is less than or equal to 9 ppm/° C. A glass transition temperature of the compound layer is larger than 150° C. The plurality of metal layers comprises a first titanium layer, a first nickel layer, a silver layer, a second nickel layer, and a metallic layer. In a first example, the metallic layer is a second titanium layer. In a second example, the metallic layer is a Titanium Nitride (TiN) layer.

    WAFER LEVEL CHIP SCALE SEMICONDUCTOR PACKAGE
    5.
    发明申请
    WAFER LEVEL CHIP SCALE SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220278076A1

    公开(公告)日：2022-09-01

    申请号：US17750118

    申请日：2022-05-20

    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

    Inventor： Yan Xun Xue ,  Madhur Bobde ,  Long-Ching Wang ,  Bo Chen

    IPC: H01L23/00 ,  H01L21/683 ,  H01L21/78

    Abstract: A wafer level chip scale semiconductor package comprises a device semiconductor layer, a backside metallization layer, a film laminate layer, and a metal layer. The device semiconductor layer comprises a plurality of metal electrodes disposed on a front surface of the device semiconductor. Each side surface of the backside metallization layer is coplanar with a corresponding side surface of the device semiconductor layer. Each side surface of the metal layer is coplanar with a corresponding side surface of the film laminate layer. A surface area of a back surface of the backside metallization layer is smaller than a surface area of a front surface of the metal layer.

    Semiconductor package having mold locking feature
    8.
    发明授权
    Semiconductor package having mold locking feature 有权

    公开(公告)号：US12142548B2

    公开(公告)日：2024-11-12

    申请号：US17566294

    申请日：2021-12-30

    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

    Inventor： Yan Xun Xue ,  Long-Ching Wang ,  Xiaoguang Zeng ,  Mary Jane R. Alin ,  Hailin Zhou ,  Guobing Shen

    IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

    Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles comprising a first die paddle. The first die paddle comprises one or more through holes, one or more protrusions with grooves on top surfaces of the one or more protrusions, or one or more squeezed extensions. Each of the one or more through holes is filled with a respective portion of the molding encapsulation. Each of the one or more through holes may be of a rectangular shape, a rectangular shape with four filleted corners, a circular shape, or an oval shape. Each of the grooves is filled with a respective portion of the molding encapsulation. A respective side wall of each of the one or more squeezed extensions is of a swallowtail shape. The swallowtail shape directly contacts the molding encapsulation.

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