TECHNOLOGY TO MINIMIZE THE NEGATIVE IMPACT OF CACHE CONFLICTS CAUSED BY INCOMPATIBLE LEADING DIMENSIONS IN MATRIX MULTIPLICATION AND CONVOLUTION KERNELS WITHOUT DIMENSION PADDING
Abstract:
Systems, apparatuses and methods may provide for technology that determines a ratio of floating point instructions to memory read instructions and controls a dimension size of a matrix kernel based at least in part on the ratio. In one example, the matrix kernel conducts an operation between a first matrix and a second matrix and the technology reuses elements of the first matrix for multiple vector lines of the second matrix.
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