Invention Application
- Patent Title: TECHNOLOGY TO MINIMIZE THE NEGATIVE IMPACT OF CACHE CONFLICTS CAUSED BY INCOMPATIBLE LEADING DIMENSIONS IN MATRIX MULTIPLICATION AND CONVOLUTION KERNELS WITHOUT DIMENSION PADDING
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Application No.: US17764114Application Date: 2019-12-16
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Publication No.: US20220350863A1Publication Date: 2022-11-03
- Inventor: Yong Wu , Xiaodong LIN , Zhong CAO , Feng YUAN , Hongzhen LIU
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- International Application: PCT/CN2019/125599 WO 20191216
- Main IPC: G06F17/16
- IPC: G06F17/16 ; G06F17/15 ; G06F12/0864

Abstract:
Systems, apparatuses and methods may provide for technology that determines a ratio of floating point instructions to memory read instructions and controls a dimension size of a matrix kernel based at least in part on the ratio. In one example, the matrix kernel conducts an operation between a first matrix and a second matrix and the technology reuses elements of the first matrix for multiple vector lines of the second matrix.
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