Invention Application
- Patent Title: COMPRESSED WALLACE TREES IN FMA CIRCUITS
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Application No.: US17358722Application Date: 2021-06-25
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Publication No.: US20220365751A1Publication Date: 2022-11-17
- Inventor: Aditya Varma , Mahesh Kumashikar , Michael Espig
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Priority: IN202141021768 20210514
- Main IPC: G06F7/53
- IPC: G06F7/53 ; G06F7/502 ; G06F15/80

Abstract:
An embodiment of an apparatus comprises one or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree, and circuitry coupled to the one or more fractional width FMA circuits to provide one or more fractional width FMA operations through the one or more fractional width FMA circuits. Other embodiments are disclosed and claimed.
Information query
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