Invention Application
- Patent Title: LOW LATENCY SSD READ ARCHITECTURE WITH MULTI-LEVEL ERROR CORRECTION CODES (ECC)
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Application No.: US17694657Application Date: 2022-03-14
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Publication No.: US20220374152A1Publication Date: 2022-11-24
- Inventor: Zongwang LI , Jing YANG , Marie Mai NGUYEN , Mehran ELYASI , Rekha PITCHUMANI
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
A storage unit is disclosed. The storage unit may include storage for a component codeword. The component codeword may be stored in a block in the storage. The block may also store a block codeword. An interface may receive a read request for a chunk of data from a host and may send the chunk of data to the host. A circuit may read the component codeword from the block in the storage. An error correcting code (ECC) decoder may determine the chunk of data based at least in part on the component codeword.
Public/Granted literature
- US12067254B2 Low latency SSD read architecture with multi-level error correction codes (ECC) Public/Granted day:2024-08-20
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