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    LOW-DENSITY PARITY-CHECK (LDPC) DECODER OF RECONSTRUCTION-COMPUTATION-QUANTIZATION (RCQ) APPROACH FOR A STORAGE DEVICE
    3.
    发明申请
    LOW-DENSITY PARITY-CHECK (LDPC) DECODER OF RECONSTRUCTION-COMPUTATION-QUANTIZATION (RCQ) APPROACH FOR A STORAGE DEVICE 有权

    公开(公告)号：US20220103187A1

    公开(公告)日：2022-03-31

    申请号：US17204936

    申请日：2021-03-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Linfang WANG ,  Rekha PITCHUMANI ,  Zongwang LI

    IPC: H03M13/11 ,  H03M13/00

    Abstract: A device is disclosed. The device may include an input buffer to receive a first low bit width message. A reconstruction circuit may implement a reconstruction function on the first low bit width message, producing a first high bit width message. A computation circuit may implementing a computation function on the first high bit width message, producing a second high bit width message. A quantization circuit may implementing a quantization function on the second high bit width message, producing a second low bit width message. A decision buffer may then store the second low bit width message. The reconstruction function and the quantization function may vary depending on an iteration and a layer of the device.

    SYSTEMS AND METHODS FOR COMPUTATIONAL ACCELERATION
    4.
    发明公开
    SYSTEMS AND METHODS FOR COMPUTATIONAL ACCELERATION 审中-公开

    公开(公告)号：US20240152466A1

    公开(公告)日：2024-05-09

    申请号：US18092925

    申请日：2023-01-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Marie Mai NGUYEN ,  Rekha PITCHUMANI ,  Zongwang LI ,  Yang Seok KI

    IPC: G06F12/109

    CPC classification number: G06F12/109 ,  G06F2212/1041

    Abstract: A system is described. The system may include a host processor, a host memory connected to the host processor, and a storage device connected to the host processor. An accelerator may communicate with the host processor. The accelerator may produce an output. The accelerator may also include a local memory, which may include a first region and a second region. The first region of the local memory of the accelerator may support a first mode, and the second region of the local memory of the accelerator may support a second mode. The accelerator may store the output of the accelerator in a destination, which may include the host memory, the storage device, the first region of the local memory of the accelerator, or the second region of the local memory of the accelerator.

    SYSTEM ARCHITECTURE PROVIDING END-TO-END PERFORMANCE ISOLATION FOR MULTI-TENANT SYSTEMS
    6.
    发明申请
    SYSTEM ARCHITECTURE PROVIDING END-TO-END PERFORMANCE ISOLATION FOR MULTI-TENANT SYSTEMS 有权

    公开(公告)号：US20220147392A1

    公开(公告)日：2022-05-12

    申请号：US17189245

    申请日：2021-03-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changho CHOI ,  Rajinikanth PANDURANGAN ,  Ramzi AMMARI ,  Zongwang LI ,  Yang Seok KI

    IPC: G06F9/50 ,  G06F9/455

    Abstract: A system is disclosed. The system may include a processor. The system may also include a first submission queue (SQ) and a second SQ. The first SQ may be associated with a first Quality of Service (QoS) level and the second SQ may be associated with a second QoS level, the first QoS level being different from the second QoS level. An application may be running on the processor and using a first namespace (NS). The processor may be configured to receive a first Non-Volatile Memory (NVM) Set create command to establish a first NVM Set associated with the first SQ. The processor may be further configured to receive a second NVM Set create command to establish a second NVM Set associated with the second SQ. The processor may be further configured to receive a first NS create command to establish a first NS associated with the first NVM Set. The processor may be further configured to receive a second NS create command to establish a second NS associated with the second NVM Set. The processor may be further configured to place an input/output (I/O) request sent from the application to at least one storage device in the first SQ based at least in part on the I/O request being associated with the first NS, the first NS being associated with the first NVM Set, and the first NVM Set being associated with the first SQ.

    SYSTEMS, METHODS, AND APPARATUS FOR DEVICES WITH MEMORY AND STORAGE CONFIGURATIONS
    7.
    发明公开
    SYSTEMS, METHODS, AND APPARATUS FOR DEVICES WITH MEMORY AND STORAGE CONFIGURATIONS 审中-公开

    公开(公告)号：US20240361952A1

    公开(公告)日：2024-10-31

    申请号：US18427816

    申请日：2024-01-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Rekha PITCHUMANI ,  Yang Seok KI ,  Zongwang LI ,  Marie Mai NGUYEN ,  Tong ZHANG

    IPC: G06F3/06

    CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A device may include cache media, storage media, a communication interface configured to communicate with the cache media and the storage media, and at least one control circuit to configure a portion of the storage media as visible memory, and configure a portion of the cache media as a cache for the portion of the storage media. The portion of the storage media may be a first portion of the storage media, and the at least one control circuit may be to configure a second portion of the storage media to persist the portion of the cache media. The portion of the storage media may be a first portion of the storage media, and the at least one control circuit may be to configure a second portion of the storage media as visible storage.

    SYSTEMS, METHODS, AND APPARATUS FOR MEMORY ACCESS IN STORAGE DEVICES
    9.
    发明申请
    SYSTEMS, METHODS, AND APPARATUS FOR MEMORY ACCESS IN STORAGE DEVICES 有权

    公开(公告)号：US20230050808A1

    公开(公告)日：2023-02-16

    申请号：US17494823

    申请日：2021-10-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Zongwang LI ,  Tong ZHANG ,  Rekha PITCHUMANI ,  Yang Seok KI

    IPC: G06F3/06 ,  G06F13/16 ,  G06F9/54

    Abstract: A method for memory access may include receiving, at a device, a first memory access request for a parallel workload, receiving, at the device, a second memory access request for the parallel workload, processing, by a first logical device of the device, the first memory access request, and processing, by a second logical device of the device, the second memory access request. Processing the first memory access request and processing the second memory access request may include parallel processing the first and second memory access requests. The first logical device may include one or more first resources. The method may further include configuring the first logical device based on one or more first parameters of the parallel workload. The method may further include allocating one or more first resources to the first logical device based on at least one of the one or more first parameters of the parallel workload.

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