An apparatus for data storage includes an interface and a processor. The interface is configured to communicate with a memory device that includes (i) a plurality of memory cells and (ii) a data compression module. The processor is configured to determine a maximal number of errors that are required to be corrected by applying a soft decoding scheme to data retrieved from the memory cells, and based on the maximal number of errors, to determine an interval between multiple read thresholds for reading Code Words (CWs) stored in the memory cells for processing by the soft decoding scheme, so as to meet following conditions: (i) the soft decoding scheme achieves a specified decoding capability requirement, and (ii) a compression rate of the compression module when applied to confidence levels corresponding to readouts of the CWs, achieves a specified readout throughput requirement.