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公开(公告)号：US11520661B1
公开(公告)日：2022-12-06
申请号：US17372568
申请日：2021-07-12
申请人： Apple Inc.
发明人： Michael Jeffet , Itay Sagron , Nir Tishbi
摘要： An apparatus includes a memory and one or more processors. The memory includes multiple memory blocks. The one or more processors are configured to read at least part of data stored in a group of one or more memory blocks, the data including multiple code words of an Error Correction Code (ECC) that is decodable using one or more processing elements selected from among multiple predefined processing elements. The one or more processor are further configured to decode one or more of the code words, and identify one or more of the predefined processing elements that actually participated in decoding the respective code words, and, based on cost-values associated with the identified processing elements, the cost-values are indicative of processing latencies respectively incurred by the identified processing elements, to make a decision of whether or not to refresh the one or more memory blocks in the group.
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公开(公告)号：US20200005873A1
公开(公告)日：2020-01-02
申请号：US16202127
申请日：2018-11-28
申请人： Apple Inc.
发明人： Eli Yazovitsky , Assaf Shappir , Itay Sagron , Meir Dalal
摘要： A storage device includes storage circuitry and multiple memory cells. The memory cells are organized in multiple memory blocks of a nonvolatile memory. The storage circuitry is configured to define a partial verification scheme that specifies testing only a data portion of the data programmed to the memory blocks, to program data to a memory block, calculate redundancy data over the data, and save the calculated redundancy data in a dedicated memory, to verify that the data portion specified for the memory block in the partial verification scheme has been programmed successfully, to check a predefined condition for conditionally performing full verification to the memory block, when the predefined condition is fulfilled, to verify that data programmed to the memory block and not tested using the partial verification scheme has been programmed successfully, and to recover, using the redundancy data, at least part of the data programmed that failed verification.
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公开(公告)号：US10339324B2
公开(公告)日：2019-07-02
申请号：US15387699
申请日：2016-12-22
申请人： Apple Inc.
发明人： Assaf Shappir , Itay Sagron
IPC分类号： G06F21/60 , G11C11/56 , G06F21/86 , G06F21/75 , G06F21/62 , G06F21/79 , G11C7/24 , G11C16/22 , G11C29/50 , G11C29/44
摘要： An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory including multiple memory cells that store data as respective analog values. The memory is addressable using physical addresses. The storage circuitry is configured to perform a first read operation from a physical address, and determine a first sequence of analog values retrieved by the first read operation, to further perform a second read operation from the physical address, and determine a second sequence of analog values retrieved by the second read operation, to evaluate a variation between the first sequence and the second sequence, and to determine that an unauthorized re-programming to the physical address has occurred between the first read operation and the second read operation, in response to the evaluated variation exceeding a predefined variation level.
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公开(公告)号：US10740476B2
公开(公告)日：2020-08-11
申请号：US16379817
申请日：2019-04-10
申请人： Apple Inc.
发明人： Assaf Shappir , Itay Sagron
IPC分类号： G06F21/60 , G11C11/56 , G06F21/86 , G06F21/75 , G06F21/62 , G06F21/79 , G11C7/24 , G11C16/22 , G11C29/50 , G11C29/44
摘要： An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory including multiple memory cells that store data as respective analog values. The memory is addressable using physical addresses. The storage circuitry is configured to perform a first read operation from a physical address, and determine a first sequence of analog values retrieved by the first read operation, to further perform a second read operation from the physical address, and determine a second sequence of analog values retrieved by the second read operation, to evaluate a variation between the first sequence and the second sequence, and to determine that an unauthorized re-programming to the physical address has occurred between the first read operation and the second read operation, in response to the evaluated variation exceeding a predefined variation level.
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公开(公告)号：US20200005874A1
公开(公告)日：2020-01-02
申请号：US16202130
申请日：2018-11-28
申请人： Apple Inc.
发明人： Assaf Shappir , Barak Baum , Itay Sagron , Roman Guy , Guy Ben-Yehuda , Stas Mouler
摘要： A controller includes an interface and a processor. The interface is configured to communicate with a nonvolatile memory including multiple memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The processor is configured to store first data in one or more WLs of a memory block, the first data occupies less than a maximal number of WLs available in the memory block, to calculate redundancy data over the first data and store the redundancy data in a dedicated memory, to program second data to a selected WL of the memory block that was not programmed with the first data, to check a programming status resulting from the programming of the selected WL, and in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, to recover the first data using the redundancy data.
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公开(公告)号：US20190236288A1
公开(公告)日：2019-08-01
申请号：US16379817
申请日：2019-04-10
申请人： Apple Inc.
发明人： Assaf Shappir , Itay Sagron
IPC分类号： G06F21/60 , G06F21/79 , G06F21/86 , G11C29/50 , G11C16/22 , G11C7/24 , G11C11/56 , G06F21/62 , G06F21/75
CPC分类号： G06F21/602 , G06F21/60 , G06F21/6245 , G06F21/75 , G06F21/79 , G06F21/86 , G11C7/24 , G11C11/5635 , G11C11/5642 , G11C16/22 , G11C29/50 , G11C2029/4402 , G11C2029/5002
摘要： An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory including multiple memory cells that store data as respective analog values. The memory is addressable using physical addresses. The storage circuitry is configured to perform a first read operation from a physical address, and determine a first sequence of analog values retrieved by the first read operation, to further perform a second read operation from the physical address, and determine a second sequence of analog values retrieved by the second read operation, to evaluate a variation between the first sequence and the second sequence, and to determine that an unauthorized re-programming to the physical address has occurred between the first read operation and the second read operation, in response to the evaluated variation exceeding a predefined variation level.
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7.发明授权公开(公告)号：US11556416B2
公开(公告)日：2023-01-17
申请号：US17558622
申请日：2021-12-22
申请人： Apple Inc.
发明人： Nir Tishbi , Itay Sagron
摘要： An apparatus for data storage includes an interface and a processor. The interface is configured to communicate with a memory device that includes (i) a plurality of memory cells and (ii) a data compression module. The processor is configured to determine a maximal number of errors that are required to be corrected by applying a soft decoding scheme to data retrieved from the memory cells, and based on the maximal number of errors, to determine an interval between multiple read thresholds for reading Code Words (CWs) stored in the memory cells for processing by the soft decoding scheme, so as to meet following conditions: (i) the soft decoding scheme achieves a specified decoding capability requirement, and (ii) a compression rate of the compression module when applied to confidence levels corresponding to readouts of the CWs, achieves a specified readout throughput requirement.
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8.发明申请公开(公告)号：US20220374308A1
公开(公告)日：2022-11-24
申请号：US17558622
申请日：2021-12-22
申请人： Apple Inc.
发明人： Nir Tishbi , Itay Sagron
摘要： An apparatus for data storage includes an interface and a processor. The interface is configured to communicate with a memory device that includes (i) a plurality of memory cells and (ii) a data compression module. The processor is configured to determine a maximal number of errors that are required to be corrected by applying a soft decoding scheme to data retrieved from the memory cells, and based on the maximal number of errors, to determine an interval between multiple read thresholds for reading Code Words (CWs) stored in the memory cells for processing by the soft decoding scheme, so as to meet following conditions: (i) the soft decoding scheme achieves a specified decoding capability requirement, and (ii) a compression rate of the compression module when applied to confidence levels corresponding to readouts of the CWs, achieves a specified readout throughput requirement.
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公开(公告)号：US20210264980A1
公开(公告)日：2021-08-26
申请号：US16799874
申请日：2020-02-25
申请人： Apple Inc.
发明人： Itay Sagron , Assaf Shappir
摘要： A controller includes an interface and storage circuitry. The interface is configured to communicate with a memory device that includes multiple memory cells organized in memory blocks. The memory device supporting programming of the memory cells with enabled or disabled program-verification. The storage circuitry is configured to disable the program-verification, and program data to a group of the memory cells in a Single Level Cell (SLC) mode using a single programming pulse, to read the data from the group of the memory cells. In response to detecting a failure in reading the data, the storage circuitry is configured to distinguish between whether the memory cells in the group belong to a defective memory block or were under-programmed, and when identifying that the memory cells in the group were under-programmed, to perform a corrective action to prevent under-programming in subsequent program operations to the memory cells in the group.
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公开(公告)号：US20170220280A1
公开(公告)日：2017-08-03
申请号：US15008470
申请日：2016-01-28
申请人： APPLE INC.
发明人： Barak Rotbard , Itay Sagron
IPC分类号： G06F3/06
CPC分类号： G06F3/0625 , G06F3/064 , G06F3/0673 , G11C16/30
摘要： A controller includes an interface and a processor. The interface is configured to communicate with one or more memory devices that include multiple memory blocks. The processor is configured to hold information regarding power consumption of the memory blocks, to group at least some of the memory blocks into one or more storage groups, based on the information, such that the memory blocks in each storage group jointly consume less than a predefined power limit when the memory blocks in the storage group are applied a storage operation in parallel, and to apply the storage operation, in parallel, to the memory blocks in a selected storage group.
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