Invention Application
- Patent Title: Multi-block Cache Fetch Techniques
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Application No.: US17324800Application Date: 2021-05-19
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Publication No.: US20220374359A1Publication Date: 2022-11-24
- Inventor: Winnie W. Yeung , Cheng Li
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Main IPC: G06F12/0811
- IPC: G06F12/0811 ; G06F12/0846 ; G06F12/0891 ; G06F12/02 ; G06F13/16

Abstract:
Techniques are disclosed relating to multi-block fetches for cache misses. In some embodiments, cache tag circuitry maintains a tag value that is shared by multiple cache blocks. In response to a miss, the cache may initiate a fetch request to a next level cache or memory. Aggregation circuitry may aggregate multiple fetch requests for cache blocks that share the tag value and fetch circuitry may initiate a single multi-block fetch operation to the next level cache or memory that returns cache blocks for the aggregated multiple fetch requests. In various embodiments, disclosed techniques may improve performance (e.g., by reducing fetch bus transactions), reduce power consumption, or both, relative to traditional techniques.
Public/Granted literature
- US12248399B2 Multi-block cache fetch techniques Public/Granted day:2025-03-11
Information query
IPC分类: