Invention Application
- Patent Title: PROCESSING SYSTEM AND CORRESPONDING METHOD OF OPERATION
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Application No.: US17737570Application Date: 2022-05-05
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Publication No.: US20220374530A1Publication Date: 2022-11-24
- Inventor: Rosalino CRITELLI
- Applicant: STMICROELECTRONICS S.r.l.
- Applicant Address: IT Agrate Brianza
- Assignee: STMICROELECTRONICS S.r.l.
- Current Assignee: STMICROELECTRONICS S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Priority: IT102021000012821 20210518
- Main IPC: G06F21/60
- IPC: G06F21/60 ; G06F21/85 ; H04L9/06 ; G06F13/16 ; G06F9/46

Abstract:
A master device issues memory burst transaction requests via an interconnection bus to fetch data from a slave device. A cipher engine is coupled to the interconnection bus and decrypts the fetched data to produce plaintext data for the master device. The cipher engine selectively operates according to a stream cipher operation mode, or a block cipher operation mode. The cipher engine is configured to stall a read data channel of the interconnection bus between the slave device and the master device in response to the cipher engine switching from the block cipher operation mode to the stream cipher operation mode. The read data channel is reactivated in response to a last beat of a read burst of the plaintext data produced by the cryptographic engine.
Public/Granted literature
- US12174973B2 Processing system and corresponding method of operation Public/Granted day:2024-12-24
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