High Bandwidth Content Addressable Memory (CAM) Based Hardware Architecture For Datacenter Networking
Abstract:
A communication protocol system is provided for reliable transport of packets. A content addressable memory hardware architecture including a reorder engine and a retransmission engine may be utilized for the reliable transport of the packets. The content addressable memory module includes a primary CAM that may be logically partitioned into a plurality of physical sub-CAMs. One or more processors are in communication with the content addressable memory module. The one or more processors receive a set of data packets. A lookup operation is performed by the one or more processors to access data entries stored in each of the sub-content addressable memories. An update operation is performed by the one or more processors at a selected sub-content addressable memory from the plurality of the sub-content addressable memories.
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