Invention Application
- Patent Title: Method and Apparatus for Estimating Signal Related Delays in a PLD Design
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Application No.: US17740644Application Date: 2022-05-10
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Publication No.: US20220382945A1Publication Date: 2022-12-01
- Inventor: Jonathan W. Greene , Gabriel Barajas , Fei Li , Hassan Hassan , James Sumit Tandon
- Applicant: Microchip Technology Inc.
- Applicant Address: US AZ Chandler
- Assignee: Microchip Technology Inc.
- Current Assignee: Microchip Technology Inc.
- Current Assignee Address: US AZ Chandler
- Main IPC: G06F30/347
- IPC: G06F30/347

Abstract:
A method and apparatus for estimating signal related delays in a PLD design is disclosed. The PLD design is modeled in relation to one or more stages, each of the stages including a driver and one or more receivers coupled to the driver with a wiring tree. The modeling is based on a selected set of parameters that include: slope related delays associated with the driver; a delay related to a layout of the wiring tree; and a parameter related to a slope transfer from a previous driver input. A predetermined set of values for each of the selected parameters are accessed; the estimated signal related delays are computed for each of the modeled stages; and are written to a computer-readable storage medium.
Information query