公开(公告)号：US20230116391A1

公开(公告)日：2023-04-13

申请号：US17852304

申请日：2022-06-28

Applicant: Microchip Technology Inc.

Inventor： Aaron Severance ,  Jonathan W. Greene ,  Joel Vandergriendt

IPC: G06F9/30

Abstract: A method and apparatus for embedding a microprocessor in a programmable logic device (PLD), where the microprocessor has a logic unit that can operate in two modes. A first mode is a general purpose mode running at least one general purpose process related to the PLD, and a second mode is a fixed function mode emulating a fixed function for use by logic configured into a fabric of the PLD (fabric). A memory unit is coupled to the logic unit and to the fabric, and the fabric is operable for transferring signals with the logic unit in relation to the fixed function.

公开(公告)号：US12223322B2

公开(公告)日：2025-02-11

申请号：US17852304

申请日：2022-06-28

Applicant: Microchip Technology Inc.

Inventor： Aaron Severance ,  Jonathan W. Greene ,  Joel Vandergriendt

IPC: G06F9/30

Abstract: A method and apparatus for embedding a microprocessor in a programmable logic device (PLD), where the microprocessor has a logic unit that can operate in two modes. A first mode is a general purpose mode running at least one general purpose process related to the PLD, and a second mode is a fixed function mode emulating a fixed function for use by logic configured into a fabric of the PLD (fabric). A memory unit is coupled to the logic unit and to the fabric, and the fabric is operable for transferring signals with the logic unit in relation to the fixed function.

公开(公告)号：US20220376693A1

公开(公告)日：2022-11-24

申请号：US17529522

申请日：2021-11-18

Applicant: Microchip Technology Inc.

Inventor： Jonathan W. Greene ,  Marcel Derevlean

IPC: H03K19/17728 ,  H03K19/21 ,  H03K19/17736

Abstract: A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y≠q, where q is a pre-determined value (e.g., such as 0 or 1).

公开(公告)号：US11671099B2

公开(公告)日：2023-06-06

申请号：US17529522

申请日：2021-11-18

Applicant: Microchip Technology Inc.

Inventor： Jonathan W. Greene ,  Marcel Derevlean

IPC: H03K19/17736 ,  H03K19/17728 ,  H03K19/21

CPC classification number: H03K19/17728 ,  H03K19/17736 ,  H03K19/21

Abstract: A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y≠q, where q is a pre-determined value (e.g., such as 0 or 1).

公开(公告)号：US20220382945A1

公开(公告)日：2022-12-01

申请号：US17740644

申请日：2022-05-10

Applicant: Microchip Technology Inc.

Inventor： Jonathan W. Greene ,  Gabriel Barajas ,  Fei Li ,  Hassan Hassan ,  James Sumit Tandon

IPC: G06F30/347

Abstract: A method and apparatus for estimating signal related delays in a PLD design is disclosed. The PLD design is modeled in relation to one or more stages, each of the stages including a driver and one or more receivers coupled to the driver with a wiring tree. The modeling is based on a selected set of parameters that include: slope related delays associated with the driver; a delay related to a layout of the wiring tree; and a parameter related to a slope transfer from a previous driver input. A predetermined set of values for each of the selected parameters are accessed; the estimated signal related delays are computed for each of the modeled stages; and are written to a computer-readable storage medium.