Invention Application
- Patent Title: MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT
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Application No.: US17852165Application Date: 2022-06-28
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Publication No.: US20230009384A1Publication Date: 2023-01-12
- Inventor: Frederick A. Ware , John Eric Linstadt , Torsten Partsch
- Applicant: Rambus Inc.
- Applicant Address: US CA San Jose
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G11C7/10 ; G11C7/22 ; G11C11/4076 ; G11C11/4096 ; G06F13/16 ; G11C7/06 ; H01L25/065

Abstract:
First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.
Public/Granted literature
- US11914888B2 Memory component with input/output data rate alignment Public/Granted day:2024-02-27
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