Invention Publication
- Patent Title: PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
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Application No.: US17836453Application Date: 2022-06-09
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Publication No.: US20230154544A1Publication Date: 2023-05-18
- Inventor: Yongsung Cho
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Priority: KR 20210158925 2021.11.17
- Main IPC: G11C16/24
- IPC: G11C16/24 ; G11C16/26

Abstract:
A memory device includes a memory cell array, and a page buffer circuit connected to the memory cell array through a plurality of bit lines, including a plurality of page buffers arranged in correspondence with the bit lines and each of which includes a sensing node. The plurality of page buffers include a first page buffer, and the first page buffer includes: a first sensing node configured to sense data by corresponding to a first metal wire at a lower metal layer; and a second metal wire electrically connected to the first metal wire and at an upper metal layer located above the lower metal layer, and a boost node corresponding to a third metal wire adjacent to the second metal wire of the upper metal layer and configured to control a boost-up and a boost-down of a voltage of the first sensing node.
Public/Granted literature
- US12057173B2 Page buffer circuit and memory device including the same Public/Granted day:2024-08-06
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