中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

37 records (took 0.024 seconds)

    Memory device, operation method of memory device, and page buffer included in memory device
    1.
    发明授权
    Memory device, operation method of memory device, and page buffer included in memory device 有权

    公开(公告)号：US12073915B2

    公开(公告)日：2024-08-27

    申请号：US17888661

    申请日：2022-08-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho ,  Min Hwi Kim ,  Ji-Sang Lee

    IPC: G11C7/20 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12

    CPC classification number: G11C7/20 ,  G11C7/065 ,  G11C7/1039 ,  G11C7/12

    Abstract: Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.

    Page buffer circuit and memory device including the same
    2.
    发明授权
    Page buffer circuit and memory device including the same 有权

    公开(公告)号：US12073909B2

    公开(公告)日：2024-08-27

    申请号：US18085963

    申请日：2022-12-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho ,  Jinwoo Park ,  Hyunjun Yoon ,  Yoonhee Choi

    IPC: G11C16/06 ,  G11C7/06 ,  G11C7/10 ,  G11C16/34

    CPC classification number: G11C7/065 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/3404

    Abstract: A memory device includes a memory cell array, a page buffer circuit, and a counting circuit. The page buffer circuit includes a first and second page buffer columns connected to the memory cell array. The first page buffer column includes a first page buffer unit and the second page buffer column includes a second page buffer unit in a first stage. The first page buffer unit performs a first sensing operation in response to a first sensing signal, and the second page buffer unit performs a second sensing operation in response to a second sensing signal. The counting circuit counts a first number of memory cells included in a first threshold voltage region from a result of the first sensing operation, and counts a second number of memory cells included in a second threshold voltage region from a result of the second sensing operation.

    Page buffer circuit and memory device including the same
    4.
    发明授权
    Page buffer circuit and memory device including the same 有权

    公开(公告)号：US11842790B2

    公开(公告)日：2023-12-12

    申请号：US18125260

    申请日：2023-03-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho ,  Inho Kang ,  Taehyo Kim ,  Jeunghwan Park ,  Jinwoo Park

    IPC: G11C7/10 ,  G11C7/12

    CPC classification number: G11C7/1039 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/12

    Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

    PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
    5.
    发明公开
    PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230154544A1

    公开(公告)日：2023-05-18

    申请号：US17836453

    申请日：2022-06-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho

    IPC: G11C16/24 ,  G11C16/26

    CPC classification number: G11C16/24 ,  G11C16/26

    Abstract: A memory device includes a memory cell array, and a page buffer circuit connected to the memory cell array through a plurality of bit lines, including a plurality of page buffers arranged in correspondence with the bit lines and each of which includes a sensing node. The plurality of page buffers include a first page buffer, and the first page buffer includes: a first sensing node configured to sense data by corresponding to a first metal wire at a lower metal layer; and a second metal wire electrically connected to the first metal wire and at an upper metal layer located above the lower metal layer, and a boost node corresponding to a third metal wire adjacent to the second metal wire of the upper metal layer and configured to control a boost-up and a boost-down of a voltage of the first sensing node.

    PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
    6.
    发明公开
    PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230143829A1

    公开(公告)日：2023-05-11

    申请号：US17965004

    申请日：2022-10-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho ,  Min-Hwi Kim ,  Makoto Hirano

    IPC: G11C16/24 ,  G06F12/0802

    CPC classification number: G11C16/24 ,  G06F12/0802 ,  G11C16/0483

    Abstract: A memory device includes a memory cell array and a page buffer circuit, wherein the page buffer circuit includes page buffer units including upper page buffer units and lower page buffer units and cache units arranged between the upper page buffer unit and the lower page buffer units. The cache units include upper cache units and lower cache units. Each page buffer unit includes a sensing node and a pass transistor. The upper cache units share a first combined sensing node, and, the lower cache units share a second combined sensing node. In a data transmission period, sensing nodes respectively included the page buffer units are electrically connected to one another through serial connections of the pass transistors respectively included in the page buffer units.

    PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
    8.
    发明公开
    PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230223056A1

    公开(公告)日：2023-07-13

    申请号：US18125260

    申请日：2023-03-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho ,  Inho Kang ,  Taehyo Kim ,  Jeunghwan Park ,  Jinwoo Park

    IPC: G11C16/24 ,  H10B80/00 ,  G11C16/04

    CPC classification number: G11C16/24 ,  H10B80/00 ,  G11C16/0483

    Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

    Page buffer circuits and nonvolatile memory devices including the same
    10.
    发明授权
    Page buffer circuits and nonvolatile memory devices including the same 有权

    公开(公告)号：US11600336B2

    公开(公告)日：2023-03-07

    申请号：US17332350

    申请日：2021-05-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung Cho ,  Byungkwan Chun

    IPC: G11C16/24 ,  G11C16/04 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A nonvolatile memory device includes a memory cell array including memory cells and a page buffer circuit. The page buffer circuit includes page buffer units and cache latches. The cache latches are spaced apart from the page buffer units in a first horizontal direction, and correspond to respective ones of the plurality of page buffer units. Each of the page buffer units includes a pass transistor connected to each sensing node and driven in response to a pass control signal. The page buffer circuit being configured to perform a data transfer operation, based on performing a first data output operation to output data, provided from a first portion of page buffer units, from a first portion of cache latches to a data input/output (I/O) line, the data transfer operation configured to dump sensed data from a second portion of page buffer units to a second portion of cache latches.

Patent Agency Ranking