- 专利标题: DISPLAY SUBSTRATE, TESTING METHOD THEREFOR AND PREPARATION METHOD THEREFOR, AND DISPLAY PANEL
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申请号: US17921898申请日: 2021-06-01
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公开(公告)号: US20230171998A1公开(公告)日: 2023-06-01
- 发明人: Yong ZHUO , Yanxia XIN , Hongwei HU , Zheng BAO , Xueping LI , Yihao WU , Xiaoyun WANG , Zhongqian GUO
- 申请人: Chengdu BOE Optoelectronics Technology Co., Ltd. , BOE Technology Group Co., Ltd.
- 申请人地址: CN Chengdu, Sichuan
- 专利权人: Chengdu BOE Optoelectronics Technology Co., Ltd.,BOE Technology Group Co., Ltd.
- 当前专利权人: Chengdu BOE Optoelectronics Technology Co., Ltd.,BOE Technology Group Co., Ltd.
- 当前专利权人地址: CN Chengdu, Sichuan
- 优先权: CN 2010574076.0 2020.06.22
- 国际申请: PCT/CN2021/097624 2021.06.01
- 进入国家日期: 2022-10-27
- 主分类号: H10K59/121
- IPC分类号: H10K59/121 ; H10K71/70 ; H10K59/12 ; H10K59/131
摘要:
Provided are a display substrate, a testing method therefor and a preparation method therefor, and a display panel, which are used for improving the success rate of transistor testing. The display substrate comprises a base substrate and a pixel circuit, wherein the pixel circuit comprises an active layer, a first gate insulating layer, a first gate electrode layer, a second gate insulating layer, a second gate electrode layer, a first interlayer insulating layer, a source/drain electrode layer, and a second interlayer insulating layer. The pixel circuit is divided into a plurality of transistors, and further comprises a gate electrode contact hole and a source/drain electrode contact hole. The source/drain electrode layer comprises a gate electrode test pad which is electrically connected to the first gate electrode layer by means of the gate electrode contact hole, and a source electrode and a drain electrode which are electrically connected to the active layer by means of the source/drain electrode contact hole. The second interlayer insulating layer is provided with a gate electrode test hole and a source/drain electrode test hole, wherein the gate electrode test hole exposes the gate electrode test pad, and the source/drain electrode test hole exposes part of an area in the source/drain electrode layer other than the gate electrode test pad.
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