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公开(公告)号：US20220320240A1
公开(公告)日：2022-10-06
申请号：US17425733
申请日：2021-01-25
发明人： Zheng BAO , Gong CHEN , Kangguan PAN , Yanxia XIN , Hongwei HU , Xueping LI , Yihao WU , Xiaoyun WANG , Yong ZHUO , Zhongqian GUO
IPC分类号： H01L27/32
摘要： A display panel includes a substrate, a plurality of data lines, at least one circle of barrier wall structure, and a connector. The substrate includes a display area, and a peripheral area which surrounds the display area and includes a fan-out area. The plurality of data lines are located on one side of the substrate and in the display area, extending from the display area to the fan-out area. The at least one circle of barrier wall structure surrounds the display area, and at least a part of the at least one circle of barrier wall structure is located in the fan-out area. The connector is located between the plurality of data lines and the barrier wall structure, and one end, away from the substrate, of the connector extends into the barrier wall structure to fasten the barrier wall structure.
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2.发明公开公开(公告)号：US20230171998A1
公开(公告)日：2023-06-01
申请号：US17921898
申请日：2021-06-01
发明人： Yong ZHUO , Yanxia XIN , Hongwei HU , Zheng BAO , Xueping LI , Yihao WU , Xiaoyun WANG , Zhongqian GUO
IPC分类号： H10K59/121 , H10K71/70 , H10K59/12 , H10K59/131
CPC分类号： H10K59/1213 , H10K71/70 , H10K59/1216 , H10K59/1201 , H10K59/131
摘要： Provided are a display substrate, a testing method therefor and a preparation method therefor, and a display panel, which are used for improving the success rate of transistor testing. The display substrate comprises a base substrate and a pixel circuit, wherein the pixel circuit comprises an active layer, a first gate insulating layer, a first gate electrode layer, a second gate insulating layer, a second gate electrode layer, a first interlayer insulating layer, a source/drain electrode layer, and a second interlayer insulating layer. The pixel circuit is divided into a plurality of transistors, and further comprises a gate electrode contact hole and a source/drain electrode contact hole. The source/drain electrode layer comprises a gate electrode test pad which is electrically connected to the first gate electrode layer by means of the gate electrode contact hole, and a source electrode and a drain electrode which are electrically connected to the active layer by means of the source/drain electrode contact hole. The second interlayer insulating layer is provided with a gate electrode test hole and a source/drain electrode test hole, wherein the gate electrode test hole exposes the gate electrode test pad, and the source/drain electrode test hole exposes part of an area in the source/drain electrode layer other than the gate electrode test pad.
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