Invention Publication
- Patent Title: MAXIMUM CURRENT SUPPRESSION FOR POWER MANAGEMENT IN A MULTI-CORE SYSTEM
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Application No.: US17866483Application Date: 2022-07-16
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Publication No.: US20230176645A1Publication Date: 2023-06-08
- Inventor: Hung-Wei Wu , Chih-Yu Chang
- Applicant: MediaTek Inc.
- Applicant Address: TW Hsinchu City
- Assignee: MediaTek Inc.
- Current Assignee: MediaTek Inc.
- Current Assignee Address: TW Hsinchu City
- Main IPC: G06F1/3296
- IPC: G06F1/3296 ; G06F1/3206

Abstract:
A management circuit is coupled to multiple processor cores for performing current suppression. The management circuit includes a detection circuit and a throttle signal generator. The detection circuit is operative to receive an activity signal from each processor core, and estimate a total current consumed by the plurality of processor cores based on activity signals. The activity signal indicates a current index proportional to current consumption of the processor core in a given time period. The throttle signal generator is operative to assert or de-assert throttle signals to the processor cores, one processor core at a time, based on one or more metrics calculated from the total current.
Public/Granted literature
- US11989077B2 Maximum current suppression for power management in a multi-core system Public/Granted day:2024-05-21
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