公开(公告)号：US11989077B2

公开(公告)日：2024-05-21

申请号：US17866483

申请日：2022-07-16

Applicant: MediaTek Inc.

Inventor： Hung-Wei Wu ,  Chih-Yu Chang

IPC: G06F1/32 ,  G06F1/3206 ,  G06F1/3296 ,  G06F1/3203

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3203

Abstract: A management circuit is coupled to multiple processor cores for performing current suppression. The management circuit includes a detection circuit and a throttle signal generator. The detection circuit is operative to receive an activity signal from each processor core, and estimate a total current consumed by the plurality of processor cores based on activity signals. The activity signal indicates a current index proportional to current consumption of the processor core in a given time period. The throttle signal generator is operative to assert or de-assert throttle signals to the processor cores, one processor core at a time, based on one or more metrics calculated from the total current.

公开(公告)号：US20180174359A1

公开(公告)日：2018-06-21

申请号：US15379529

申请日：2016-12-15

Applicant: MediaTek Inc.

Inventor： Ying-Chieh Chen ,  Shih-Chin Lin ,  Chih-Yu Chang

IPC: G06T17/20 ,  G06T15/00 ,  G06T1/60

CPC classification number: G06T1/60 ,  G06T11/40 ,  G06T15/005 ,  G06T2210/08 ,  H04N19/00 ,  H04N19/436 ,  H04N19/587

Abstract: A graphics system provides frame difference generator hardware for dynamically adjusting a frame rate. The graphics system includes a graphics processing unit (GPU), which generates frames containing tiles of graphics data. The frame difference generator hardware receives the graphics data of a tile of a current frame from the GPU, in parallel with a frame buffer that also receives the graphics data. The frame difference generator hardware computes a difference value between a first value computed from the graphics data and a second value representing a corresponding tile of a previous frame, and accumulates difference values computed from multiple tiles of the current frame and the previous frame to obtain an accumulated value. The accumulated value is reported to software executed by the graphics system for determination of an adjustment to the frame rate.

公开(公告)号：US20170308988A1

公开(公告)日：2017-10-26

申请号：US15134279

申请日：2016-04-20

Applicant: MediaTek Inc.

Inventor： Yen-Hsiang Li ,  Jih-Ming Hsu ,  Yen-Lin Lee ,  Chih-Yu Chang ,  Chiung-Fu Chen ,  Chih-Chung Cheng ,  Chung-Min Kao ,  Che-Ming Hsu

IPC: G06T1/20 ,  G06T3/60 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T3/60 ,  G06T11/40

Abstract: A graphics accelerator device offloads the workload of a graphics processing unit (GPU) by performing image composition and other specialized functions. The graphics accelerator device includes a rasterization module to rasterize a set of primitives to a set of pixels and generate information of the set of pixels. The graphics accelerator device also includes intra-process module to retrieve pixel values from a memory according to the information received from the rasterization module, perform mathematical calculations on the pixel values, and generate one or more processed image layers. The graphics accelerator device further includes an inter-process module to composite the one or more processed image layers received from the intra-process module with other image layers retrieved from the memory, and output a composited image to a display.

公开(公告)号：US10282806B2

公开(公告)日：2019-05-07

申请号：US15134279

申请日：2016-04-20

Applicant: MediaTek Inc.

Inventor： Yen-Hsiang Li ,  Jih-Ming Hsu ,  Yen-Lin Lee ,  Chih-Yu Chang ,  Chiung-Fu Chen ,  Chih-Chung Cheng ,  Chung-Min Kao ,  Che-Ming Hsu

IPC: G06T1/20 ,  G06T3/60 ,  G06T1/60

Abstract: A graphics accelerator device offloads the workload of a graphics processing unit (GPU) by performing image composition and other specialized functions. The graphics accelerator device includes a rasterization module to rasterize a set of primitives to a set of pixels and generate information of the set of pixels. The graphics accelerator device also includes intra-process module to retrieve pixel values from a memory according to the information received from the rasterization module, perform mathematical calculations on the pixel values, and generate one or more processed image layers. The graphics accelerator device further includes an inter-process module to composite the one or more processed image layers received from the intra-process module with other image layers retrieved from the memory, and output a composited image to a display.

公开(公告)号：US20230176645A1

公开(公告)日：2023-06-08

申请号：US17866483

申请日：2022-07-16

Applicant: MediaTek Inc.

Inventor： Hung-Wei Wu ,  Chih-Yu Chang

IPC: G06F1/3296 ,  G06F1/3206

CPC classification number: G06F1/3296 ,  G06F1/3206

Abstract: A management circuit is coupled to multiple processor cores for performing current suppression. The management circuit includes a detection circuit and a throttle signal generator. The detection circuit is operative to receive an activity signal from each processor core, and estimate a total current consumed by the plurality of processor cores based on activity signals. The activity signal indicates a current index proportional to current consumption of the processor core in a given time period. The throttle signal generator is operative to assert or de-assert throttle signals to the processor cores, one processor core at a time, based on one or more metrics calculated from the total current.